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DAC3xJ8x EVM SPI via FMC connector

Ana S
Prodigy 65 points
Other Parts Discussed in Thread: DAC37J82, LMK04828, DAC38J84

Hi,

I am working on a demo design with DAC37J82 EVM connected to a board with Lattice ECP5 FPGA through FMC connector.

I would like to use FPGA to configure the DAC37J82 and LMK04828 over the SPI interface via FMC connector.

I shorted 1-2 of the JP3, and I see that SPI signals are passing through the FMC to the CPLD but I am not sure if anything is written to the registers since all I get on SPI readout are zeros from both the DAC and LMK. I am trying to configure them in 4-wire SPI mode.

I am driving the FMC_SCLK, FMC_SDO, FMC_SEN_DAC, FMC_SEN_LMK signals, but I've noticed that the FMC_DIR_CONTROL also toggles when using SPI over USB. What are the requirements for this signal? What about FMC_B5 and FMC_B6 signals?

Is it maybe possible to get the CPLD design source code?


Thank you and regards,

Ana

  • 0
    Prodigy 120 points

    By default, these devices come up in 3 wire SPI mode. Did you turn on the 4 wire SPI mode that enables the MISO line?

    Check register 2 bit 7.

  • 0
    TI__Guru 66104 points
    Hi Ana,

    I will need to ping the team to find out more regarding using FMC connector for SPI control. I hope to have some preliminary answer for you some times next week.
  • 0 in reply to Kang Hsia
    Prodigy 65 points

    Hi Kang,


    any news on this issue? I have an update. I've noticed that the DAC_SDIO and LMK_SDIO  (pins 35 and 76 of the CLPD)  are low even though I'm driving the FMC_SDIO (pin 3 of the CPLD). So it seems that the CPLD isn't passing the FMC SDIO input to the DAC and LMK SDIO outputs (those are bidirectional pins on the DAC and LMK chips, so CPLD probably requires another control signal to decide on the direction). FMC_SCLK, FMC_SEN_DAC and FMC_SEN_LMK are driven ok by the CPLD.

    Bill, yes, bit 7 of the DAC config2 register is set to 1.


    Thank you and regards,

    Ana

  • 0 in reply to Ana S
    TI__Guru 66104 points

    Hello Ana,

    Sorry for the late response. Currently we have only verified the FTDI path (USB), but not FMC path. I have attached the CPLD file for you to review. It may be possible that some modification may need to be made. 

    DAC38J84EVM_CPLD.qar

    DAC38J84_CPLD.v

    The following information is based on the currrent FTDI path and hopefully it can help you debug the FMC path. 

    You may use the attached "DAC38J84.txt" file to determine the patterns needed for the SPI transaction. It may be best viewed in Excel spreadsheet. The same can be applied to the LMK04828 chip.

    DAC38J84.txt 
    Write																																																			
0	0	0	1	0	1	0	1	0	1	0	1	0	1	0	1	0	1	0	1	0	1	0	1	0	1	0	1	0	1	0	1	0	1	0	1	0	1	0	1	0	1	0	1	0	1	0	1	0	1	0	0
1	0	0	0	1	1	A13	A13	A12	A12	A11	A11	A10	A10	A9	A9	A8	A8	A7	A7	A6	A6	A5	A5	A4	A4	A3	A3	A2	A2	A1	A1	A0	A0	D7	D7	D6	D6	D5	D5	D4	D4	D3	D3	D2	D2	D1	D1	D0	D0	0	0
2	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1
4	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1
5	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
6	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
7	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1
																																																			
Read																																																			
0	0	0	1	0	1	0	1	0	1	0	1	0	1	0	1	0	1	0	1	0	1	0	1	0	1	0	1	0	1	0	1	0	1	0	1	0	1	0	1	0	1	0	1	0	1	0	1	0	0	0	0
1	0	1	1	1	1	A13	A13	A12	A12	A11	A11	A10	A10	A9	A9	A8	A8	A7	A7	A6	A6	A5	A5	A4	A4	A3	A3	A2	A2	A1	A1	A0	A0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
2	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	D7	D7	D6	D6	D5	D5	D4	D4	D3	D3	D2	D2	D1	D1	D0	D0	0	0
3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1
4	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1
5	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
6	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
7	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1
    LMK04828.txt 
    Write																																																			
0	0	0	1	0	1	0	1	0	1	0	1	0	1	0	1	0	1	0	1	0	1	0	1	0	1	0	1	0	1	0	1	0	1	0	1	0	1	0	1	0	1	0	1	0	1	0	1	0	1	1	0
1	0	0	0	0	0	0	0	A12	A12	A11	A11	A10	A10	A9	A9	A8	A8	A7	A7	A6	A6	A5	A5	A4	A4	A3	A3	A2	A2	A1	A1	A0	A0	D7	D7	D6	D6	D5	D5	D4	D4	D3	D3	D2	D2	D1	D1	D0	D0	0	0
2	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
3	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1
4	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	1
5	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
6	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
7	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1
																																																			
Read																																																			
0	0	0	1	0	1	0	1	0	1	0	1	0	1	0	1	0	1	0	1	0	1	0	1	0	1	0	1	0	1	0	1	0	1	0	1	0	1	0	1	0	1	0	1	0	1	0	1	0	1	1	0
1	0	1	1	0	0	0	0	A12	A12	A11	A11	A10	A10	A9	A9	A8	A8	A7	A7	A6	A6	A5	A5	A4	A4	A3	A3	A2	A2	A1	A1	A0	A0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
2	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
3	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1
4	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	1
5	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
6	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	D7	D7	D6	D6	D5	D5	D4	D4	D3	D3	D2	D2	D1	D1	D0	D0	0	0
7	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	1

    The first column indicates FTDI FT2232 (U3) CD bus bits. We have been using CD bus for both DAC38J84 and LMK04828 devices. For instance, 0 stands for CDBUS0 of pin38 of U3.

    You may see row 0 is the SCLK pattern. row 1 is the SDIO write process. row 2 is reading back part of the SDIO read process in three wire mode. row 3 is the SDENB process where it is held high at all time and pulled low during SPI transaction. 

    Other details includes:

    ·         “Ax” indicates “bit x of the address to be written” for both the read and write case. The address is always written for both reading and writing.       Example: A5 refers to 5th address bit(starting from A0)

    ·         “Dx” indicates “bit x of the data to be written” for writing and “bit x of the data to be read” in the read case. The data is written for writing and read for reading.

    ·         The address length and data length for each device is extracted from the file based on the largest address bit and largest data bit (i.e. A31 indicates a 32 bit address).

    ·         Except for the pin from where the read bits are received, all other pins are configured to be output pins.

    -Kang