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DAC3484EVM sync signal question

adeel asif
Prodigy 110 points
Other Parts Discussed in Thread: DAC3484, CDCE62005

Hello,

    I am using DAC3484 EVM with xilinx VC707 board. Data is coming to DAC at 200 MHz data clock.  With interpolation 1x, dac clock is also 200 MHz which is coming from on board PLL. The problem is that fifo collision alarm is going high.

   I am using sync signal for both fifo read and write pointer reset. Sync signal is a periodic signal. It is 1 for 15 cycles and zero for 16th data clk cycle and then again 1 from 17th cycle to 31.

Is this correct sequence for sync signal? or should I do like  :

sync signal is periodic signal with sync = 1 for 1 data clock cycle and zero for 15 data clock cycles and so on?

Following are register values

x00    x0098
   x01    x010E
   x02    xF000
   x03    xF000
   x04    xFEFE
   x05    x3F78
   x06    x3000
   x07    xFFFF
   x08    x0000
   x09    x8000
   x0A    x0000
   x0B    x0000
   x0C    x0400
   x0D    x0400
   x0E    x0400
   x0F    x0400
   x10    x0000
   x11    x0000
   x12    x0000
   x13    x0000
   x14    x0000
   x15    x0000
   x16    x0000
   x17    x0000
   x18    x280F
   x19    x0440
   x1A    x0020
   x1B    x0000
   x1C    x0000
   x1D    x0000
   x1E    x1111
   x1F    x1144
   x20    x1100
   x22    x1B1B
   x23    xFFFF
   x24    x0000
   x25    x7A7A
   x26    xB6B6
   x27    xEAEA
   x28    x4545
   x29    x1A1A
   x2A    x1616
   x2B    xAAAA
   x2C    xC6C6
   x2D    x0004
   x2E    x0000
   x2F    x0000
   x30    x0000
   x7F    x0004
CDCE62005 Registers
Freq:0.000000MHz
Address Data
00 00400000
01 81800321
02 81800302
03 80400003
04 00040004
05 28241BD5
06 04AE1996
07 150035F7
08 20001C08

 

  • 0
    TI__Guru 66114 points
    Adeel,

    Since you are using the single sync source mode, we recommend you set up the FPGA to send a one time rising edge for the FIFO synchronization. The setup/hold time and the duration of the pulse are described by the timing diagram on Figure 52 to Figure 55 of the datasheet. Note that Tframe_sync is 1/2 of dataclk cycle.

    You may refer to the following app note for details of setting up your DAC3484.
    www.ti.com/.../slaa584

    -Kang
  • 0 in reply to Kang Hsia
    Prodigy 110 points

    With your approach i was getting fifo collision alarm. I made sync signals periodic. It was a single cycle pulse which became high after 15 clock cycles. Also, I used FPGA clock from PLL on DAC EVM instead of clock on VC707.