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ADC16V130 grounding dilemma??

Gauraw Srivastava90
Prodigy 185 points
Other Parts Discussed in Thread: ADC16V130

Hi,

    I am using ADC16V130 in my design and as per ADC grounding discussion i have one solid ground plane for the my card.I am operating at about 42MHz and input signal is of 70MHz.Best ENOB i could achieve is only 10.5 bits.ADC interfaces to a FPGA sitting on other card through FMC connector.My colleges in my company say that because card has single ground and it is directly connected to noisy digital card through connector so noise floor of the ADC card is same as of digital card.Now i am planning for Re-CAD of the card with separate analog and digital  ground planes and connecting DRGND pin to DGND.Will it help?? and if yes then will it be required to short AGND and DGND.    

  • 0
    TI__Expert 4340 points

    Gauraw,

    I recommend continuing to have a solid, single GND plane under the ADC and analog signal path. If the logic/FPGA circuit or other downstream digital is dumping too much noise on the GND plane, then I recommend splitting the GND plane between the ADC and logic device. AGND and DGND will continue to be a single plane under the ADC. WIth this new GND split, you must be concerned about signals that must transition from one GND reference plane to the other. If you use tightly coupled differential traces for the ADC data lanes and cross the split at a perpendicular angle, the you should be OK. Be sure that the ADC supplies are all referenced to the proper GND plane. If single ended signals must cross the GND split (such as SPI signals) then cross at a perpendicular angle keep away from other critical signals.

    Regards, Josh 

  • 0
    Prodigy 150 points

    Hi Gauraw,

    thank you for your question. Would be great to read one day if an AGND did help you.

    May I ask you how you calculated your ENOBs. We are in the same situation with the '160 version and still trying to figure out how to qualify the board by measuring the ENOBs. A quick outline how you did it would help.

    Best Regards, Florian

  • 0 in reply to Florian Busch
    TI__Expert 4340 points

    Florian,

    There has been an interesting discussion on the calculation of ENOB here:

    http://e2e.ti.com/support/data_converters/high_speed_data_converters/f/68/t/434460 

    Regards, Josh

  • 0 in reply to Joshua Carnes
    Prodigy 185 points

    Thanxs Joshua for your reply.But i have one more doubt.LVDS buffer section of ADC has separate ground (DRGND) and supply pin (VDR) and i was planning to connect DRGND to digital ground of the card which also the ground for logic/FPGA.I that way i need not cross the ground split for ADC data.The supply reference for VDR will be DRGND only and isolated from ADC ground(AGND).Will this scheme create any degradation in performance for ADC??

  • 0 in reply to Joshua Carnes
    Prodigy 150 points
    Hi Josh,

    thanks for the link, but I actually started the discussion. But it was basically how to interpret the WaveVision numbers.

    It is still unclear – and this is why I was hoping on Gauraw for some help – how to extract the ENOB of an ADC in the system.

    Is there a proposed way (by TI) to extract the ENOBs of an ADC once it is assembled on the customer’s board ???

    Best Regards, Florian
  • 0 in reply to Florian Busch
    Prodigy 185 points
    Hi Florian,
    For ENOB we captured sufficient samples in the FPGA for single tone pure sine wave.We made sure that ADC is getting -1dBFS power by observing the bit ocupancy in FPGA.Then by using a MATLAB script we plot the waveform and calculate ENOB. I hope my approach solves your problem.
  • 0 in reply to Gauraw Srivastava90
    Prodigy 150 points
    Sounds great, Gauraw,

    I was hoping to read in the samples in WaveVision, but have file-import problems there.

    May I ask you, when you say you plot the waveform and calculate the ENOB, are you doing it by using the plot or do you go the hard way and calculate the spectrum power etc.

    I try to go the hard way, as LeCroy [1] suggests, but that’ll gonna be a pain. I’ll also try a MatLab script as well [2].

    I still hope that TI has some magic MATLAB or C code to serve its community.

    Best Regards, Florian

    [1] cdn.teledynelecroy.com/.../computation_of_effective_no_bits.pdf
    [2] www.mathworks.com/.../52867-calculating-snr-for-an-a-d-system
  • 0 in reply to Gauraw Srivastava90
    TI__Expert 4340 points

    Gauraw,

    The intention of using a solid GND plane under the ADC is to prevent difiicult-to-anticipate grounding issues like ground loops and signal coupling during reference plane transitions. Connecting DRGND to a separate gnd should theoretically work, but that would require that the DGND plane be under all the LVDS pins to immediately give them the correct reference plane. The gnd planes would then be split under the ADC which can cause a number of unanticipated ground loops. It is much easier to avoid gnd loops when the gnd plane transition is done a little way away from the ADC.

    Regards, Josh

  • 0 in reply to Joshua Carnes
    Prodigy 185 points

    Thanks Josh,

                            I got your point.