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Foe zero band pass sampling, can I use ADC10D1500 directly without using zero IF conversion

usha kannikanti
Prodigy 20 points
Other Parts Discussed in Thread: ADC10D1500, LM15851

Hi I am developing a zero IF down conversion for 720 MHZ IF QPSK modulated signal (input) with band width of 320 Mbps.

For this, do I need to use the quadrature down conversion for bringing down to zero IF and then using ADC10D1500 or can I directly use the ADC10D1500 with proper sampling frequency.The final ADC outputs will go to FPGA for further processing.

Is ADC10D1500 and RF ADCs works similar? Kindly guide me to take a decision.


- Usha.

  • 0
    TI__Mastermind 43930 points

    Hi Usha

    The ADC10D1500 device could potentially support this requirement, but the complex mixing and decimation would need to be implemented inside the FPGA, and the FPGA will need to support either 48 LVDS pairs at 750 Mbit/sec or 24 LVDS pairs at 1500 Mbit/sec. The high data rate (1500 or 3000 Msamples/sec) will make it relatively complicated to implement the mixing/decimation functions.

    An alternative solution would be to use the LM15851 device. It contains a 12 bit ADC front end which can sample as fast as 4000 Msamples/sec. This is followed by an internal DDC (digital down-converter) which can do the necessary complex mixing and decimation to reduce the data rate/bandwidth down to what is needed for demodulation. This device uses the JESD204B data interface and would only need 2 to 4 pairs of high speed serial data depending on the decimation setting chosen. This approach would require an FPGA which supports the JESD204B data standard, but the I/O and processing requirements inside the FPGA would be significantly reduced.

    Best regards,

    Jim B

     

  • 0 in reply to Jim Brinkhurst1
    Prodigy 20 points

    Sir,

    My analog input is a QPSK modulated signal (centre is 720 MHz and Band width is 320 MHz i,e, the input band is 560MHz- 880MHz) . Now if I use sampling frequency to ADC as 880 MHz, I'll get the band at DC-320 MHz from ADC; then is I and Q channels of ADC 10D1500 will not give qudarature outputs?

    I am using Xilinx's Virtex 6 LX 135 FPGA. I feel any FPGA can not handle 750 Mbps data directly. Hence I do not want to do down conversion inside.

    Is LM15851 can support my band width requirement. In data sheets, I observed 800 MHz is the output band width. So if the above logic not works, kindly suggest the alternate one.

  • 0 in reply to usha kannikanti
    TI__Mastermind 43930 points

    Hi Usha

    The ADC10D1500 can operate as either 2 inputs sampled at the input clock rate (non-DES mode), or a single input sampled at 2x the input clock rate (DES mode).

    DES = Dual Edge Sampling, ie. the input signal is sampled on both edges of the input clock.

    In 2 input mode, the I and Q inputs both sample their input signals at the same time with very low skew. They are not sampled with 90 degree phase offset.

    If you use 2 input mode, you can connect your IF signal to the I input (or Q input) and if the sample rate is around 960 MSPS the input signal will be centered nicely in the 2nd Nyquist zone (480 MHz to 960 MHz).

    The output data from the ADC can be output in 1:2 Demux mode, which will be 480 Mbit/sec with DDR clocking. The DCLK will be at 240 MHz. The Virtex 6 LX can definitely handle that data rate.

    If you only use a single input, you can power down the Q channel and then only need to connect two 12-bit LVDS buses from the ADC to the FPGA.

    With the LM15851 the useful output bandwidth is BW = (Fs/Decimation) * 0.8. To achieve 320 MHz BW you can sample at 4 GSPS and use Decimate by 8 mode (400 MHz BW) or Decimate by 10 mode (320 MHz BW). In decimate by 8 mode you could scale back the sample rate to just what is needed. 3600 MSPS in Decimate by 8 mode would also give the needed BW and would keep the input signal away from the fixed interleaving spur which will be located at Fs/4.

    I believe the Virtex 6 you are using is supported by the Xilinx JESD204B IP so using the LM15851 should be possible.

    Best regards,

    Jim B