• State TI Thinks Resolved
  • Locked Locked
  • Replies 2 replies
  • Answers 1 answer
  • Subscribers 46 subscribers
  • Views 655 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Need help with configuring the DAC39J82

Layne Jakahi
Intellectual 820 points
Other Parts Discussed in Thread: DAC39J82, DAC38J82

Hello

Due to the huge set of registers, we are having a hard time with determining the correct register settings.  

First of all, we want to use the following mode as listed in Table 10 (DAC39J82 speed limits):

L = 8

M = 2

F = 1

S = 2

HD = 1

INTERPOLATION = 2

MIN FSERDES = 0.78125 Gbps

MAX FSERDES = 7 Gbps

MIN FDATA = 156.25 MSPS

MAX FDATA = 1400 MSPS

MIN FDAC = 312.5 MSPS

MAX FDAC = 2800 MSPS

MAX BW = 1120 MHZ

Based on these parameters, we need the input data rate, fDATA (or equivalently DACCLKP/N) which is seen on the left side of Figure 56 to be below to be 1320MHz and we need the DACCLK which is illustrated on the right of Figure 56 to be below to be 2640MHz.  Here we need fSERDES to be 6.6Gbps.   According to the formula on page 129 of the dac39j82 datasheet, for dual DAC, 8 lanes mode, the Serialized Data Rate per lane = fDATA*16*(10/8)*2/8 = 6.6Gbps).

Secondly, as mentioned in Table 10, we plan to use 2x interpolation and need the output sample rate fDAC to be 2640MHz.  Also we need to use the Full Complex Mixer to shift the spectrum to the left by, for example, 1/4 of the fDAC.

Based on these characteristics, how do we configure the DAC38J82.  Please assist. 

Thank you.

  • 0
    TI__Guru 66104 points

    DAC3xJ8x Configuration.pptxHi Layne,

    You could take advantage of our DAC3xJ8x GUI program to help you configure the device. You basically need to set up the DAC as you planned on the first main page, and then you can program the GUI to output the appropriate register sets. Check out the attached ppt for detail.

    -Kang

  • 0 in reply to Kang Hsia
    Intellectual 820 points

    Hello Kang,

    I hope that you are still on this forum after all this time.  If not, I hope someone on this forum can assist.

    Anyways, as it turns out, we are still seeing an intermittent problem with setting up the JESD link between our FPGA (Virtex 7) and the pair of DAC39J82.  With all the other issues, we have put this on the back burner until now.

    1) I guess one question is in relation to the Initialization Sequence shown on page 132 of the DAC39J82 datasheet.  You have illustrated this on page 3 of your powerpoint.

         For instance, in steps 8 and 10, it looks like the config 74 gets written twice (once before programming the clkjesd_div, cdrvser_sysref_mode and interp AND then again after).  Is this correct?

    2) Secondly, should we be taking the Initialization sequence literally?   For instance, for step 6, it states to write CONFIG26, CONFIG49, CONFIG50, CONFIG51.  Obviously its not in sequential order.  As it stands now, we have our firmware writing to all the registers sequentially in order...like CONFIG1, CONFIG2, CONFIG3, CONFIG4....ect.

    3) Do you have the config register settings for use with as xilinx fpga?  We are wondering if there is some kind of bug if ITEM1 and ITEM2 are not problems.

    Please assist.  Because the documentation on JESD is really broad/vague, we don't understand why our register settings dont work.  Specifically, the JESD core in the FPGA that intermittently reports that it is NOT ready.  This means that something happened to the link between the FPGA and DAC and its just not right.

    Thank you.