Hi,
I am currently interfacing my ZedBoard with your DAC 3484 EVM. And was trying now to send a simple saw tooth signal to the DAC via GUI software.
The result is not really a saw tooth (see image).
My PLL is locked. And I am using LVDS 2.5V instead of LVDS 1.8 because my FPGA board supports only LVDS 2.5V.
Do you have any idea what my is going wrong?
Thank you.
Warm regards,
Serdarrpf
Serdar,
The sine wave has to be 5MHz and above to overcome the higher pass response corner. Otherwise the sine wave may be attenuated. You may check the mini-circuits transformer datasheet for detail:
-Kang
Kang Hsia I was sending a sine wave to channel A and zeros to Channel B, C and D. But I get analog output data on all 4 channels (see image).
It seems like there is a timing issue or a synchronization problem. I really don't know why this happens, maybe you have an idea.
My simple setup:
- sending 16 bit LVDS_25 DDR data, 100Mhz clock and a SYNC signal to the DAC
- the FPGA is not capturing any signal from the DAC
I attached also my dac settings. i can not see any error. i would appreciate any kind suggestions how to solve my problem.
Thank you very much.
- data sending vhdl code:
DATA_behav: process(CLK_WIZ, RESET)
begin
if (RESET = '1' ) then
ODDR_IN_BD <= (others=>'0');
ODDR_IN_AC <= (others=>'0');
togle <= '0';
elsif (rising_edge(CLK_WIZ) ) then
if (RESET_LOCK = '1') then
togle <= not togle;
if (togle= '1')then
ODDR_IN_AC <= sine_wave_gen;
ODDR_IN_BD <= (others=>'0');
else
ODDR_IN_AC <= (others=>'0');
ODDR_IN_BD <= (others=>'0');
end if;
end if;
end if;
end process;
- SYNC signal vhdl code:
SYNC_behav: process(CLK_WIZ, RESET)
begin
if (RESET = '1' ) then
count_sync <= (others=>'0');
SYNC <= '0';
elsif (rising_edge(CLK_WIZ)) then
if (RESET_LOCK = '1') then
if(count_sync = "111") then
SYNC <= '1';
count_sync <= (others=>'0');
else
count_sync <= count_sync + 1;
SYNC <= '0';
end if;
end if;
end if;
end process;
.