Dear sirs,
we understand that the ENOB [dbFS] decreases with increased Vpp (of the signal sinus).
We tested different clocking devises (with different jitter numbers), clocking waveforms (squared vs. sinus) and different clock line filtering methods (being inspired by page 15 of TI’s SLAA510 document).
We see improvements of the ENOB when different scenarios are applied.
But here comes the question. With decreasing Vpp the difference vanishes and all graphs tend towards 12.6 ENOB (for Vpp almost 0). Please have a look at [1]. We would have expected an improvement over the complete Vpp range.
I assume the clock-line optimization is worse the few cents, but does it mean, that the ENOBs of the ADC will never be greater than 12.6 ? This is the number we can derive from the datasheet (Fig. 10 of the ADC16DV160 datasheet) and which we see in the conducted tests, using WaveVision and extrapolation ?
BTW: we use the ADC16DV160HFEB evaluation platform.
By the way, do you propose a specific oscillator for the ADC16DV160 ?
Thank you for your answer in advance,
Best Regards, Florian