Adjust the DAC3482 full scale

Hi Kang,

Our application is kind of AWG (Arbitrary Waveform Generator).
So we need to set the DAC parameters, load the data in the memory and as a final step we start the generation.
While we have active generation we don't want to change any DAC parameters.

Then at certain moment we want to stop the curent signal, load anaother signal with probably 1e3 times smaller Vpp
Is it not posible to adjust the VEXTIO/Rbias, load the new data(still close to the DAC 16 bit full scale) and start the new generation?

I understood that there may be an issue to change the VEXTIO/Rbias while we have active generation but this is actually not required in our case.

Or did I misundestood your comment?

Thanks
Dimitar

#Hi Kang,

>Basically you want to keep all the DAC parameters such as interpolation, mixers, and all you want to do is to adjust the output current level. Would you have access to at least the register programming of the coarse DAC register?

#Yes we most probably (at least for the initial version of our product ) will set all of the DAC parameters (including coarse_dac) together with loading of the signal pattern and keep those unchanged for the time signal is generated. I thought we could adjust the BIASJ current at this 'preparation' moment as well.

>Once the DAC3482 device is powered on, we cannot recommend any changes to the VEXTIO and RBIAS. The VEXTIO and RBIAS that was connected to the DAC before it was powered off must remain the same when it is powered on. You can change them again once the DAC is powered off again.

#So basically we have to reset (whatever this could mean) the DAC in between changing the signal we want to generate. Hmm this may be not very convenient.

>The best way to approach this is to set VEXTIO and RBIAS to a constant (i.e. 1.2V and 1.92kohm). This will give the maximum 30mA full-scale at start-up. Before the first active generation, adjust coarse DAC (3:0) (config3) to the full-scale current that you need. Generate the DAC output that you need. Then program the current that you need for the 2nd active generation.

#Here I think you refer to the coarse_dac 4 bit register? Note that for our application 4 bits of resolution may not be enough. Consider a situation that we want to generate 1Vpp differential output. We set our analog driver at the output of the DAC being able to do this without distortion and at the same time we use full scale of the DAC and coarse_dac =15. Then with the same hardware we want to generate signal with 1mVpp (this is way to extreme but good to illustrate my question). Now what we can do is to reduce coarse_dac =0 and therefore reduce the signal 16 times. However we need 1000 times. The additional level reduction we can do reducing our data 62.5 times and with this we loose 6 bits of the DAC resolution.
What is the best procedure we need to deal with this?

>Keep in mind that the DAC is designed with output full-scale current ranging from 10mA FS to 30mA FS. Also, at all time, you must keep the DAC output within the -0.5V to +0.6V for each leg. The compliance voltage depends on the full-scale current and the overall resistive load (i.e. V = IR).

#OK so basically what you are saying that we eventually can adjust the BIASJ current but not more then 3 times. OK in that case we have to think about some variable gain element at the output indeed.

>Programming the coarse DAC register is equivalent to changing the VEXTIO and RBIAS, and is the safer way to adjust the output full-scale current. The input data scale can remain full-scale as you desired. You just have to make sure that the output current and voltage do not exceed the recommended range.

#Yes coarse_dac seems simple to use. I just think that the 4 bit resolution may appear not enough for our application. But I think I got the idea. We will require wide band variable attenuation after the DAC if we want to improve this.

Thank you!
Dimitar

Dimitar,

Regarding the following:

>Once the DAC3482 device is powered on, we cannot recommend any changes to the VEXTIO and RBIAS. The VEXTIO and RBIAS that was connected to the DAC before it was powered off must remain the same when it is powered on. You can change them again once the DAC is powered off again.

#So basically we have to reset (whatever this could mean) the DAC in between changing the signal we want to generate. Hmm this may be not very convenient. 

You will need to power down the DAC and somehow use switches of any kind to switch the VEXTIO and RBIAS to change the BIASJ. Then you can power on the DAC again.

#Here I think you refer to the coarse_dac 4 bit register? Note that for our application 4 bits of resolution may not be enough. Consider a situation that we want to generate 1Vpp differential output. We set our analog driver at the output of the DAC being able to do this without distortion and at the same time we use full scale of the DAC and coarse_dac =15. Then with the same hardware we want to generate signal with 1mVpp (this is way to extreme but good to illustrate my question). Now what we can do is to reduce coarse_dac =0 and therefore reduce the signal 16 times. However we need 1000 times. The additional level reduction we can do reducing our data 62.5 times and with this we loose 6 bits of the DAC resolution. 
What is the best procedure we need to deal with this?

Yes, I am referring to the coarse DAC 4 bit register. This is the main programmable register for the overall full-scale current adjustment.

Honestly, I think the best way for you is to adjust your input digital scale so you can utilize the full 16-bit resolution of the DAC. If changing the 4-bit coarse DAC full-scale current is too coarse, the only way to adjust the scale finely is to adjust the digital input scale. This is the intended operation of this DAC.