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DAC38J84 -- is DTEST setting "SYNC" (0100) the same as JESD204B SYNC?

Other Parts Discussed in Thread: DAC38J84

Hi,

I've been using the DTEST setting "0100" (SYNC) to debug a JESD204B link on the DAC38J84. However, it appears this SYNC signal is *not* the same as JESD204B's SYNC signals (accessible via the SYNC_N_AB, SYNC_N_CD, and SYNCB_[PN] terminals. Can you confirm this interpretation?

If so, I'm sending constant data to my DAC and I see data-dependent (but fixed) patterns on this SYNC test signal. If they are useful indications of the DAC state, can you briefly describe them?

It would be wonderful to see a revised datasheet for this part which includes more information (and clears up the errata.)

thanks,

Graeme

  • Hello Graeme,

    You are correct. The DTEST setting of '0100' (SYNC) is not the same as the JESD204B SYNCB. The DTEST has tests for the physical layer only such as PRBS test, SERDES PLL out, etc. It does not have tests for the JESD204B layer.

    Brief investigations showed the DTEST SYNC is an indicator for each RX lane on when the synchronization alignment for the comma K28.5 patterns. I do not believe this will be extensively used in DAC38J84 products and hence I plan to remove this from the datasheet.

    Thank you for your feedback regarding the datasheet comments. I am in the process of incorporating all the changes for the datasheet revision.

    -Kang
  • Hi Kang,

    Thanks for the prompt reply. We are now in a working state with the DAC38J84 -- wow, this was a frustrating part to bring up! It is a complicated device, though, and some amount of pain is expected. Thanks for your time and assistance.

    I'll pass along any extra errata I see in the datasheet. Two additional comments / requests:

    First, it would be nice to know exactly what conditions trigger a "link configuration error" condition. The Quick Setup step provided by the GUI disables this check, and I haven't been able to enable it successfully despite a pretty thorough review of both the FPGA and DAC sides of the link. A short list of possible sources would help me track down the problem.

    Second, there's very little information and no example code (that I can find) about performing eye scans on the DAC. We have eye scans from our ADC (implemented on the FPGA), but a DAC eye scan would give us some indication that our PCB stackup and layout is acceptable and the links are well tuned. Can you point me in the right direction?

    cheers,
    Graeme
  • Hi Graeme,

    Thanks for the feedback.

    Regarding your comments:
    1. will need to brainstorm and compile a list of conditions. Need to get back to you on this.

    2. The use of eye scan requires JTAG set up. I have drafted some preliminary document that will go on the next datasheet revision. I have private messaged you. Please accept the request so I can send you the document.

    -Kang