help with 37J82 DAC EVM with KC705 board

Inhwan,

If you go the TSW14J10EVM project folder on the TI website, you can download firmware that is used to integrate the DAC3xJ8x board with a KC705 platform using the TSW14J10EVM. This firmware will give you a working example that uses the latest Xilnx JESD204B IP core. For help with the memory and FIFO issues you are having, consult your local Xilinx applications engineer.

Regards,

Jim 

Thank for the comment Jim

I am working on each project (DAC/ADC) for now

yes, of course I will move on that example soon if I can fix this problem first.

So far, I have figured out how DAC/ADC GUI is configured.

It seems like it is getting better everyday.

Anyway, I have one more question (it can be critical or not)

I just come up with one concern based on clock assertion sequence.

From the past experiment, ref clk & core clk should be set in GUI.

then the bit file (image for FPGA) has to be downloaded into KC705.

Otherwise, it doesn't work (loopback test & test pattern)

I am wondering how I can manage that problem.

Is it any other possible way to download image first, then set up for "clock"s in GUI?

Thank you

Hi Kang Hsia
thank you for comment
I just realized how to use GUI setting, but not 100 %
DAC tutorial is not specific enough to do some experiment with DAC EVM board

Anyway, now I almost done with my experiment.
I checked out the data from loopback & normal streaming operation by using some pattern
it seems like it works fine.
But, now, I have one more concern.
I think the FPGA image has to be downloaded first, before GUI clock setup
When I tried to setup GUI for clock after I downloaded FPGA image into KC705, the data doesn't stream in & out.
in other words, i don't see any data streaming through debugger

Do you have any suggestion for this problem?
Thank you

Inhwan,

Xilinx has informed us that after the firmware is loaded and then the ref and core clks are applied, you will need to do a soft register reset. This is address 0x004 and you write a "1" to bit 0. It is a self clearing register but may take several usec before it clears. This is documented in their JESD204B app notes.

Regards,

Jim

Hi,

I'm also trying to connect a DAC37J82EVM to a Xilinx KC705. Is there a tutorial on how to set this up? Are there any reference designs for the KC705? Also, do I need to have the TSW14J01 in order to interface to the KC705 like in figure 1 of JESD204_TI_reference_design.pdf? Or can I just connect to it directly?

Andrew

Andrew,

You will need the TSW14J10EVM if you want to use HSDC Pro GUI. If you plan on using your own GUI to send the data, you could connect the board directly to the KC705. The TSW14J10EVM User's Guide, found under the TSW14J10EVM product folder on the TI website, has an example of operating the DAC38J84 with the KC705.

Regards,

Jim

Hi Jim,

Do you have a version that will work with 2014.4?

Andrew

Andrew,

Unfortunately not. This was provided by Xilinx and it would take some work. Below is a comment we received from Xilinx in the past: 

"To update the script for 2014.2 the work is trivial.

But…

To update it to 2014.3/2014.4 will be quite difficult. We completely changed the internal structure of the IP so the hand customized files used by this script are obsolete".

I would suggest contacting your local Xilinx FAE for support regarding this.

 

Regards,

Jim

Hi Jim,

I've built the reference design for the KC705 in 2015.1 without the  TSW14J10EVM . Do you have a walkthrough of what commands to send to the DAC to generate a pattern on the output?

Andrew

DAC38J84_442_368.64.pptxAndrew,

Follow the attached example or the DAC example at the end of the TSW14J10 User's Guide, which you can download from the TI website. 

Regards,

Jim

Hi Jim,

I followed section 6.1 DAC38J84EVM GUI Setup Example to setup the board but I can't connect to the board via the High Speed Data Converter Pro 4.10. The steps I took were:

1) built the vivado project

2) program the bitstream and run the tsw program in the SDK. I can see output on the serial port. After title it says platform ID = 0x27

3) run the dac3XJ8J GUI v1.1 and says it's connected. Change the EVM clocking mode to onboard. Interpolation to 1. LMK04828 clock outputs for DCLK Divider 0 to 8 and DCLK Divider 12 to 16. Unchecked Group powerdown for CLKout 12

4) Opened HSDC v4.10 and noticed that it wasn't connected. I tried connecting to the board via instrument options as well as unplugging and replugging the USB cable. Nothing has worked so far.

What am I doing wrong?

Andrew

i'm running windows 8.1 by the way

Andrew,

HSDC Pro has not been tested with Windows 8. Can you try a machine that has Windows 7?

Regards,

Jim

Andrew,

You need the TSW14J10 to run HSDC Pro. How were you connecting the USB without this board?

Regards,

Jim

Hi Jim,

I just connected the DAC to the KC705 via the FMC. 

I tried it with a windows 7 machine and it also failed.

Is there a walkthrough of what commands to send to the DAC to generate a pattern on the output without the TSW14J10EVM? For instance, by hard coding the bit commands in the Vivado SDK? 

ANdrew

Andrew,

The DAC GUI will do this for you. Just follow the two examples I sent. My question is why do you mention HSDC Pro GUI? This cannot be used without the TSDW14J10. How are you programming the FPGA to output data to the DAC? If you doing something custom, are you monitoring the error messages on the DAC using the DAC GUI? Are you able to establish a valid link connection? 

Regards,

Jim

Hi Jim,

I mentioned HSDC Pro because slide 4 of your powerpoint shows a 10MHz DAC test pattern loaded via the HSDC pro GUI. The TSW14J10 User's guide says the same. Do I just ignore this slide/step?

So far I've not been able to output any data from the DAC. I'm not doing anything custom, just following the slides and the TSW14J10 User's guide section 6.1.  I think I have a connection to the DAC via its usb port because when I disconnect it, the DAC GUI complains about the lack of connection. 

Andrew

Andrew,

What firmware are you using for the FPGA?

Regards,

Jim

Hi Jim,

The firmware I'm using I found under TI_HSDC_Pro_Reference_design_V2.7/sw_src/tsw/src. I generated the bistream from the script/build_it.tcl after modifying it for the KC705.

Andrew

Andrew,

There is no walk through for using the DAC directly connected to the KC705. It is highly recommended that you first get the system working with the KC705+TSW14J10 to verify that you have a working system and do your DAC evaluation using the KC705. You can do a lot of testing and evaluation using this system before you move to a direct connection without using the TSW14J10.

Once you are at the point of bypassing the TSW14J10, you will need to work with Xilinx apps directly to make it work. We are not resourced properly to support custom FPGA firmware builds.

Ken.

Andrew,

With this bitstream, you need to use the TSW14J10EVM. Do you have one? This firmware if used as is was designed to be used with the TSW14J10. Did you modify the firmware at all? What application is this for?

Regards,

Jim 

Hi Ken,

Thanks for clarifying that. I assume that to connect the KC705 to the DAC directly there needs to be a series of commands written to the DAC to get it working. Is this correct? If so, what are they?

Hi Jim,

I do not have a TSW14J10EVM and I didn't modify the firmware at all. 

Andrew

Andrew,

You need to purchase a TSW14J10EVM or modify the firmware.

Regards,

Jim

Hi Jim,

Do you have any information or resources on how to modify the firmware (eg what commands the KC705 needs to send to the DAC)?

Andrew

Andrew,

What application is this for? Based on this info, we may be able to send you a free TSW14J10EVM and more support. Otherwise, your best bet is to look at the existing firmware and documentation and design your own pattern generator. These are the best resources we can offer.

Regards,

Jim

Hi Jim,

The application is for the military. I'd greatly appreciate a free TSW14J10EVM but I noticed that they are not in stock when I tried to buy them. Do you have any lying around?

Andrew

Andrew,
The commands to the DAC are SPI writes from the DAC GUI to configure the DAC in a certain mode. Those SPI writes are done through the USB connection on the DAC EVM. You can see what resgisters are being written by double clicking the lower left corner of the DAC GUI - this will open the register command window. When you click program/reset/trigger buttons as per the bring up guide, you can see all of the SPI commands that go to the DAC and the LMK device. This is nothing to do with the firmware and only configures the DAC.

If you are working directly connected to the FPGA you can follow the same DAC programming sequence using the DAC GUI. The TSW14J10 allows HSDC Pro a means to configure the firmware registers to match the JESD204B configuration in the DAC. If you are not using TSW14J10 or HSDC Pro, then you will need to provide a firmware with the JESD204B IP block already setup for the appropriate DAC configuration.

Ken.

Andrew,

Let's take this correspondence off line. My email is j-seton@ti.com. Please send me your address and we will ship you a board.

Regards,

Jim