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ADC12D1600 - Verifying AutoSync with time stamp

Hiroshi Katsunaga
Mastermind 6480 points
Other Parts Discussed in Thread: ADC12D1600

Hello,

My customer has a question about ADC12D1600.

[Q]

Please tell me how to verify AutoSync with time stamp in Multiple ADC application.

I am confusing why it use the DCLK_RST+/- pin in AutoSync.

What kind of design should a customer make for their board?

I read the following application notes.

  - SNAA198 : AN-2132 Synchronizing Multiple GSPS ADCs in a System : The AutoSync Feature

  - SNAA073F : From Sampling Instant to Data Output : Understanding Latency in the GSPS ADC

My understanding is as follows.

<My understanding>

- If the Sampling Instants variation cannot be guaranteed by design, TimeStamp feature is necessary.

- The TimeStamp feature can be used to verify AutoSync. -> Why?, How?

- This feature uses the LSB of the Data output to add a time stamp from a signal input at the DCLK_RST+/- pins. -> Why DCLK_RST+/- pins in AutoSync?

Best Regards,

Hiroshi Katsunaga

  • 0
    TI__Mastermind 20541 points
    HI Hiroshi,

    There are two ways to verify AutoSync function. The primary method is to monitor the DCLKs of all the ADCs. If the DCLKs of all the ADCs are on the same phase then all the ADCs are synchronized.

    The secondary method that can be used is the TimeStamp feature. In this method the TSE BIT (Addr: 0h; Bit:3) should be enabled and an external trigger should be applied at DCLK_RST input pin. And if you observe the trigger signal on the LSB of digital outputs (DQd,DQ,Did,DI). In this method you are not using DCLK_RST+/- pins to synchronize the ADC, you are using this as an input for the trigger signal.

    If the customer is using high sampling clock rates, they should drive RCLK externally. If not then they use either binary tree or daisy chain approach.

    Regards,
    Neeraj Gill
  • 0 in reply to Neeraj Gill
    Mastermind 6480 points
    Hi Neeraj,

    Thank you for your fast response.
    I understood your comment.
    However, I am not slightly clear about the TimeStamp feature.

    My understanding for the TimeStamp feature with AutoSync is as follows.

    <My understanding for the TimeStamp with AutoSync>
    - the TSE bit(Addr:0h, Bit:3) should be enabled.
    - DCLK_RST+/- is not used as sync signal, it is used as trigger signal.
    - It is necessary for the customer to input the trigger signal into the DCLK_RST+/- of each ADCs.
    - It must arrive at each ADCs at the same time, or it is necessary for the skew of the trigger signal to each ADCs to be known.
    - TimeStamp outputs the 1-bit converted value of the input to the DCLK_RST+/- pins on the LSB.
    - The frequency of the trigger signal has to be below fs/2.
    (fs means sampling frequency, <ex1> fs=1600MHz@FCLK=1600MHz, Non-DES mode, <ex2> fs=3200MHz@FCLK=1600MHz, DES mode)

    Is my understanding correct ?

    Best Regards,
    Hiroshi Katsunaga
  • 0 in reply to Hiroshi Katsunaga
    TI__Mastermind 20541 points
    Hi Hiroshi,

    All the points you mentioned are correct. I think you are understanding this right.

    Regards,
    Neeraj Gill
  • 0 in reply to Neeraj Gill
    Mastermind 6480 points

    Hi Neeraj,

    Thank you for your fast response.

    OK, I understood it.

    Thank you for your support !

    Best Regards,

    Hiroshi Katsunaga