ADC12D1600RF Calibration Issue

Hi Neeraj,

Thanks for the quick reply !! Yes it's 2.6 GSPS (not MSPS)...

Also, the ADC is configured in 1:4 Demux DES mode with DDR and the DDR Data-to-DCLK phase relationship is 0 degrees (i.e. Bit 14 of Reg 0 is set to 0).

This is the method we use to capture the ADC data :

1) The DCLK of the ADC is fed into a Mixed Mode Clock Manager to generate a buffered in phase clock at the same rate as DCLK.
2) This buffered clock is then used to sample the DDR data which are then aligned and processed further.

Do you see any issues in this method ? Does the phase of the DCLK w.r.t DDR Data change after/during calibration ? What could be other possible reasons for the FPGA not capturing the data (which might help me in debugging the issue) ?

I will also try the test pattern mode in the meanwhile..


Thanks,
Prashanth

UPDATE: I set the test mode on and here's what I observed :

1) After the ADC went crazy, the test data that was received from the ADC was completely out of order. 

2) Even though they were out of order, 95% of the data received was among of those specified in the test pattern sequence (000h, 004, 008h, 010h, fffh, ffbh, ff7h and fefh) . The rest 5% of the data were junk (eg: 00ch, cffh, 0ffh etc).

3) After the ADC recovered (powered on/off the system a couple of times), the data that was read perfectly matched the test sequence. There were no junk data received at all.

Even with calibration (on-command) turned off all the time I see this issue happening with this ADC. What do you suggest me to do next ? 

Thanks,
Prashanth

Hi Neeraj,

The reason I was getting junk data/out of order data in test pattern mode was due to an issue in my debug code. Now that is solved and I always get the correct sequence in test pattern mode (even after the ADC goes crazy). Also, I checked the voltages and they are all fine. I read out the register values too and they were all as expected.

I have a couple of other questions :

1) During run-time we change the sampling frequency (i.e. ADC clock). Does this affect the ADC in anyway ? Is there something that needs to be done (like reset ADC, set register values again or perform calibration) every time the sampling frequency is changed ? 

2) Does the power consumption of the ADC change while it is calibrating ? I couldn't find any information about this in the manual.

FYI, we have two ADCs working in Master-Slave configuration. The master provides the reference clock to the slave and hence the Autosync register values (address Eh) have been set as 0x0001 (master) and 0x0007(slave). The rest of the register values are similar for both ADCs.

Thanks,

Prashanth

Hi Neeraj,

Thanks once again for your continued assistance !!

In the last few days I have been working on this issue and here are a few things that I uncovered :

1) Instead of master-slave configuration, I configured both ADCs as master for debug purposes and I wrote exactly similar register values into both ADCs so as to compare the behaviour of the two.
2) On debugging, I found that the on-command calibration fails only for ADC1 (very consistently). However, ADC2's calibration NEVER failed.
3) I also read the calibration register (Addr : 5h) 240 times of both ADCs and compared. I see that the values of the two ADCs are completely different.
4) Then, I completely disabled on-command calibration only for ADC1, but wrote the calibration register values read from ADC2 into ADC1 (I was periodically calibrating ADC2 every 10 s and then was writing cal values read from ADC2 into ADC1 every time). To my surprise, the ADC1 never went crazy after this (tested for at least a couple of hours).

So, my questions are :

1) Why is there a huge difference in the calibration register values even though both ADCs are configured in the same way and are also operating under similar conditions ?
2) What do the 240 calibration register values really mean or correspond to ? Also, is there any specific range within which each of the cal values should lie ? I couldn't find this info in the manual.
3) Given that writing calibration register values of ADC2 into ADC1 is not causing failure of ADC1, I think it is safe to conclude that on-command calibration for ADC1 is failing. Is there any reason why you think this might happen ?

Update : I disabled on-command calibration for ADC2 and enabled calibration for ADC1. I then wrote the calibration values from ADC1 into ADC2, and as expected ADC2 also started behaving crazy. This further supports our conclusion that ADC1 calibration is failing.

Regards,
Prashanth

Hi Prashanth,

Have you tested multiple boards? if yes are you seeing this issue on other boards or this is the only board that is having issues?

I think at this point it would be best to return the ADC chip for further analysis. Here is the link to return it.

http://www.ti.com/lsds/ti/quality/resources/customer_returns.page

Answering your question.

1. All the ADCs will have different internal mismatches/performance, the calibration value for one ADC will be different than the other ADCs.

2. All the 240 values are different coefficients calculated by the ADCs to compensate for internal mismatches etc and to improve the performance of the ADCs to desired levels.

3. I don't know why the calibration on the ADC1 is failing. As I said before I have never seen this issue before. I think at this point it is best to return the ADC for further verification.

Regards,

Neeraj Gill