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dac38j84 SerDes configuration

Other Parts Discussed in Thread: DAC38J84, ADC16DX370, LMK04828, DAC38J84EVM

Hello ,

  Can the alternating 0/1 pattern with a period of 2UI (Serdes Test Modes)  be used for the SerDes lines equalization?

 We are trying to verify settings and test the SerDes lines but constantly getting EQOVER.

 I would appreciate any suggestions.

Thank you in advance.

Vlad.

 

  • Vlad,

    I may have to looking into this further. At this point, I believe that it may be best to use some sort of PRBS pattern to establish good training sequence for the DAC38J84 adaptive equalizer. The PRBS pattern have less correlation (more random) and provide more realistic frequency response for the the adaptive equalizer to adjust the gain over frequency.

    Alternating 0/1 patterns have high correlation and fixed frequency response. The actual data bandwidth for fixed pattern may be narrower than the random information pattern (i.e. fixed, impulse response vs. random, gaussian response), and I think the equalizer may try to overcompensate at the higher frequency. When the actual data pattern starts, the equalizer may provide higher gain than needed due to the wider bandwidth of random information signal. 

    Please clarify the condition and test pattern in which you get the EQOVER in equalizer training. This will help with the analysis. 

    -Kang. 

  • Hello Kang,

       We are trying to bring up a dac38j84  on our hardware. The DAC is interfaced to Kintex-7, 4-lane mode, external 2400MHz DACCLK (from LMK048280), x16 interpolation. We spent some time and the best result we could get so far is a positive test of SerDes lines with 0/1 pattern. PRBS test is failed. It might be an issue with our test firmware (FPGA) or with the lanes routing.  

     

      How the EQUNDER/EQOVER results obtained with EQ[1:0] = 10 and 11 settings (Postcursor/Precursor equalization analysis.) can be applied to the FPGA GTX settings? I trust you know that the GTX TX settings from FPGA side have Pre-/Post- cursor settings in dB.

      I would appreciate any suggestions on the DAC configuration, test/debug methodology and procedure.

      By the way, we have adc16dx370 working perfectly on the same hardware board.

     Thank you,

    Vlad.

     

  • Hello Kang,


    We are trying to bring up a dac38j84 on our hardware. The DAC is interfaced to Kintex-7, 4-lane mode, external 2400MHz DACCLK (from LMK048280), x16 interpolation. We spent some time and the best result we could get so far is a positive test of SerDes lines with 0/1 pattern. PRBS test is failed. It might be an issue with our test firmware (FPGA) or with the lanes routing.



    How the EQUNDER/EQOVER results obtained with EQ[1:0] = 10 and 11 settings (Postcursor/Precursor equalization analysis.) can be applied to the FPGA GTX settings? I trust you know that the GTX TX settings from FPGA side have Pre-/Post- cursor settings in dB.

    I would appreciate any suggestions on the DAC configuration, test/debug methodology and procedure.

    By the way, we have adc16dx370 working perfectly on the same hardware board.

    Thank you,

    Vlad.
  • Hello Kang,

       There is one more question, please.

      We still can not path any PRBS pattern SerDes test. Watching with a oscilloscope ALARM terminal we noticed that the error signal has a regular (quite periodic) structure.  Might it be that we are wrong with clock the Serdes divider/multiplier settings? With DACCLK = 2400MHz, interpolation 16, x4 lane mode we want to have 3Gbps per lane. Could you, please, confirm our settings - divider and multiplier for Serdes. Though we have SerDes PLL0 locked <config108 = 0x0007>, we still can not path through the PRBS tests. Any suggestions and/or advice on the issue will be greatly appreciated.

  • Vlad,

    Your JESDCLK and SERDES CLK dividers are set correctly. I would recommend that you use the SYSREF from the LMK04828 to sync the DAC internal clock dividers to ensure all the digital logics inside the DAC core are initialized correctly. We have the clock divider reset logic set by default to pay attention to the 2nd SYSREF pulse, assuming the same DC coupled network as the EVM.

    A while ago while debugging the Xilinx platform + DAC38J84 with one of our customers, we noticed that when both ours and their VC707 SERDES/JESD side are based on QPLL, we cannot get the DAC38J84 to pass the K28.5 training sequence. This was confirmed on both our side and their side. Only when we switched to CPLL we were able to get the K28.5 training sequence to pass. Since the K28.5 and PRBS are both non-fixed pattern, I wonder if you are seeing the same thing. Since I am not too familiar with FPGA, I am not too sure about the root cause and the latest update. You may want to touch base with Xilinx support rep regarding the PLLs to use for the IP.

    I will also ping our colleague to see if he knows the latest status. Will keep you updated.

    -Kang

  • Hi Kang,

    You wrote "we switched to CPLL". Does it mean that there is a bit in the DAC configuration which controls CPLL or QPLL?

    Where are the SerDes AC coupling capacitors for the DAC should be - at DAC or FPGA side? I noticed from both ADC 16dx370and DAC38j84 reference designs that the capacitors are in both cases are close to the chips. Does the placement - close to Rx or Tx terminals - matter?. What are TI recommendations in case of the DAC?

    Thank you,
    Vlad.
  • Hi Vlad,

    The CPLL and QPLL is referred to the Xilinx IP. Apparently at the when the Xilinx IP core has a different PLL generating the SERDES core, the K28.5 training sequence and CGS stage is fixed.

    The AC coupling cap is an AC short so the impact is minimal. Since our TSW14J56 (data pattern generator)EVM and DAC38J84 EVM is connected via FMC connector, we left the AC coupling cap on the DAC EVM side close to the SERDES receiver. The idea is that the receiver's internal termination should take care most of the reflected power so any disturbance (even due to the AC coupling cap) will not be reflected back to the transmitter.

    The DAC equalizer and the inherent 8b/10b coding should taken care of the DC wonder issue with the ac coupled network.

    If you would like, I can send you the DAC38J84 IBIS AMI model so you can incorporate you PCB design (stack-up, T-line, etc) along with our model to perform some simulations such as eye diagram, etc.

    -Kang
  • Hi Kang,

    Thank you very much for the detailed explanation.
    Now all SerDes PRBS tests are passing through meaning that PCB is Ok.

    As we can see from ChipScope now the DAC is toggling SYNCB every time at the end of ILA.

    1. Could you, please, clarify how JESD204B Pattern Test can be performed? Any special sequence of settings we should follow?

    2. Description of config 74 says : "jesd_test_seq Set to select and verify link layer test sequences. The error for these
    sequences comes out the lane alarms bit0. 1= fail and 0 = pass".
    In what register the lane alarms bit0 can be found?

    3. What type of errors are reported (and where) for jesd_test_seq = 11, repeating ILA sequence? What can we test?

    We would appreciate your any suggestions .

    Thank you in advance,
    Vlad.
  • Vlad,

    First of all, if the SYNCB is toggling constantly high -> low -> after CGS stage, this may indicate the CGS stage is never completed or there are some issue with the ILA sequence.

    One way to bypass the ILA sequence stage (for debugging purpose) is to enable config79, bit 5 (no_lane_sync). Basically, the DAC38J84 will read the ILA sequence from the FPGA and ignore it. If the CGS stage passes, the SYNCB will remain high (the DAC will not request sync anymore). If the CGS stage fails, the SYNCB will be low again to request the sync process from the FPGA.

    I will actually need to gather more information on the JESD204B link layer test from various design sources. I will have to get back to you on this. 

    -Kang

  • Hi Kang,

    Thank you very much.

    We tried to switch Off ILA (no_lane_ sync = 1). The DAC reports "bit1 = read_error : Asserted if read request with empty FIFO" error for each lane and there is no output signal.
    What might be the reason of this error?

    Thank you,

    Vlad.
  • Hi Vlad,

    We have provided some information regarding Xilinx FPGA and DAC38J84EVM with known good working setup to Jame Kay. You should receive information from him directly.

    here is the answer to your question above:
    At the DAC JESD block level, there is a FIFO to ensure correct timing between the JESD204B IP block to the rest of the digital DAC core. The fact that the FIFO is having error and reading empty suggests that the JESD204B data coming into the DAC38J84 is slower than the JESD204B being read after the FIFO. Either the FPGA’s JESD204B IP is running slower or the DAC38J84 JESD204B IP is running faster than expected
  • Hi Kang,

    Thank you very much for the details. Unfortunately, it did not help. A request with more details has been sent to James. I do not know which channel (E2E or through James) works faster. Please advise. We need to resolve the issue asap.

    Thank you in advance.
    Vlad.
  • Vlad,

    Can you send us the DAC register settings so we can try this on our setup?

    Regards,

    Jim

  • Hello Gentlemen,

    We have fixed the issue. Now the DAC is working. Thank you very much. The reason was in DAC and TX side SerDes lines start-up sequence. The SerDes lines should be active from JESD204 TX side at the moment when the DAC comes out of reset/init sequence.

    Thank everybody one more time.

    Vlad.
  • To close the question regarding JESD204B short test, please refer to the following Altera/DAC38J84 Interop Document:
    www.altera.com/.../an719.pdf

    page 10 mentioned the procedures to perform short test
  • Hi Vladimir

    I have same problem. The DAC reports "bit1 = read_error : Asserted if read request with empty FIFO" error for each lane and there is no output signal.

    can you send me register setting?

    Thank you,

    M.Kh