ADS5401 track and hold operation

Hi,

in a normal ADC, the track-and-hold consists of a capacitor to 'hold' a voltage and a switch that opens and closes with the sample clock.  During the low time of the clock, the switch is closed and the input signal is applied to the sample cap and the cap 'tracks' the input signal.  when the sample clock goes high, the switch opens and the input signal is 'frozen' on the cap at that point and the cap 'holds' that last voltage that it saw.  It is during the clock high time that the voltage on the cap is applied to the circuitry that begins to resolve the voltage to an arithmetic code.  When the clock goes low again, the sample that was captured on the cap makes its way through the pipeline of the data converter and the switch closes again to let the cap track the input signal again.   so for an entire half cycle of the clock the sampling cap 'sees' the input voltage.  At the rising edge of the clock as applied to the pin of the device, there is some buffer delay before the switch can actually be opened and this effective delay from external clock edge to the point in time where the signal is frozen on the cap is the aperture delay.  Variations of this effective sampling point from one sample to another is called aperture jitter, specified on page 9.

The above description is a bit of a simplification, pretending that the clock and voltage on the cap are single ended entities.  In reality, the signal and the clock are fully differential so there would be these switches on both sides of the differential input, and depending on the exact topology of the design there may be other switches to pre-bias internal nodes of the device to prevent interactions from one sample value to the next.    And since this is an internally interleaved device, there are really two separate sampling caps and the switches to the second sample cap has the inverse relationship to the clock.  While one sampling cap is tracking the input signal during clock low, the other sample cap is holding the sample value, and vice versa.    The sampled value from one sampling cap is latched on one edge of the clock and fed down one of the internal ADC pipeline paths while the sampled value from the other sampling cap is latched on the other edge of the clock and fed down the other of the internal ADC pipeline paths.

But each internal ADC is open to the incoming signal for half a clock cycle.  Aperture jitter is possibly the parameter you are interested in, as that is the period of uncertainty as to exactly when the sample is effectively taken.   And the larger this period of uncertainty, the lower the SNR possible from the ADC.   The externally applied clock will have its own jitter on the exact position of the clock edges applied to the device, and this external clock jitter must be taken into consideration with the internal or aperture jitter to determine the expected SNR for the overall design.  Assuming both aperture jitter and the externally applied sample clock jitter are both Gaussian, then the total effective jitter is the square root of sum of squares of the aperture jitter and external jitter.

Aperture jitter is largely not dependent on the clock rate.  Your external clock jitter may or may not be dependent on the clock rate.  The window of time the sampling caps track the incoming signal is of course dependent on clock rate, being half of a clock cycle each.

Regards,

Richard P.