ADC31JB68EVM compatibility

Ian,

Thanks for your interest in TI ADC's. We do provide HDL code for both Altera and Xilinx devices. Our data capture board for devices with JESD204 interfaces is based on the Altera Arria V. We can arrange to send you the HDL source code to you if desired.

Our designs are also compatible with Xilinx reference boards. We offer the TSW14J10EVM interposer card which allows you to connect an EVM to a Xilinx KC705 (Kintex-7) or VC707 (Virtex-7) and use our GUI and firmware to capture data. The ADC31JB68EVM would work with either; The ADS54J69 would likely require the use of the VC707. I am not aware of support for the KCU105 when using our TSW14J10EVM interposer and I do not think we have source code targeted for this platform, but the hardware connection from the EVM to the KCU705 is likely still compatible and you could start with the KC705 source code and re-target for the ultrascale platform.

Regards, Josh

Is the KC705 & VC707 the full list of Xilinx fpga boards that are fully supported?

What about the ZC706?

At this point in time, I am interested in evaluating the ADC31JB68EVM as well as the  DAC37J82EVM,

on Xilinx platforms.

But I would like to have official TI support.

Thanks!

- Ian

Ian,

If you are interested in utilizing TI's data analysis GUI (or pattern generator tool) to easily capture and analyze data, then you will need to use the TSW14J10EVM as an interposer between the device EVM and Xilinx reference board. In this case, the KC705 and VC707 are the only supported Xilinx reference boards. Example firmware source is available for these options.

If you do not require the use of TI's GUI, then the TSW14J10EVM will not be used and you are generally responsible for your own data analysis tools (though we do have a limited set of Matlab scripts you ay find useful). In this case, then you are limited only in hardware connector compatibility, so the number of supported Xilinx reference boards is expanded. The most important aspect is the number of SERDES lanes that are routed to FMC connector for the given Xilinx board. The ADC31JB68EVM has only 2 SERDES lanes @5Gb/s and the ZC706 has 8 lanes routed so this is compatible. I am 95% sure that it will be compatible with the ZC706 (where my remaining doubt is only the due diligence of looking into the small details of the design further). Example firmware is generally not available (from TI) for boards other than the KC705 and VC707, though re-targeting source code that we do have may aid in your development.

I am reasonably confident that the DAC37J82 device will also be supported by the ZC706, but I am not as familiar with the DAC. For further support of this device, please re-post your question with the DAC37J82 in the headline to attract the supporting engineer.

Thanks, Josh

Ian,

The DAC37J82EVM will not work directly with the ZC706. The DAC requires the SYNC signals to be on FMC connector pins F10/F11 or F19/F20 but the ZC706 did not route any signals to the pins. The TSW14J10 routes the SYNC signals to pins E2/E3 of the ZC706 with some jumper modifications, which will allow the DAC to work with this EVM.  

Regards,

Jim

OK, so now I am leaning towards the KC705 board, since that is officially supported.

Will the DAC37J82EVM work with the KC705 board (with or without the interposer board)?

Thanks so much!

- Ian

That's really helpful!

Now I just need to know where to download HDL for both the

 ADC31JB68EVM  & DAC37J82EVM

running with the interposer board on the Xilinx KC705 fpga board.

Thanks!!!

- Ian

Please find the download in the Software Section of

www.ti.com/.../tsw14j10evm

Regards, Josh

I now have the ADC31JB68EVM, the DAC37J82EVM, the TSW14J10EVM, and the Xilinx KC705.

The DAC37J82EVM + TSW14J10EVM + KC705 combination works.

I use the DAC3XJ8X GUI to configure the DAC, and use the HSDC Pro to control the KC705 fpga carrier via the TSW14J10EVM. Great!

Now when I try to evaluate the ADC, things are not so clear.

I do NOT see an option for downloading ADC31JB68EVM firmware from the HSDC Pro software connected to the TSW14J10EVM, and the ADC31JB68EVM manual does not mention anything about Xilinx FPGA boards.

Help please!

- Ian

Ian,

Please see the attached procedure and extra files required to run the ADC31JB68EVM+TSW14J10EVM. This has been tested with an HSDC Pro v3.0 but should still be compatible with the latest version. If you have troubles, please let me know how far you got and I'll help through the rest.

Regards, JoshTSW14J10EVM_ADC31JB68EVM.zip

Hi Josh,

the instructions and files mostly work.

The issue is that the sample rate is only *half* what is stated.

I feed in a clock at 500M, and I tell it the sample rate is 500M.

I feed in a 1MHz signal, and it only takes 250 samples to span the period of the input signal.

Further, the FFT reports that the signal is at 2MHz.

I tried sending a 2x clock (ie 1GHz), but then capture times out.

I tried adjusting the clock divide-by ratio to 2 (on the ADC31JB68EVM GUI), but that also do not solve the Fs issue.

This is with HSDCPro 4.10.

- Ian

There are more issues. Running at 480MHZ Fs,

the FFT shows signals at F, 120MHz +/- F, and 240M - F.

so there appears to be strong aliasing around Fs/2 and Fs/4.

This is of a sine wave whose frequency increases, and the aliases move at the _same rate_ as F (so not harmonics!).

- Ian

When I load the new .ini file, all the problems went away!
Thanks Joshua!!!
- Ian

Ian,

I'm pretty sure that DAC37J82EVM+TSW14J10EVM+KC705+HSDCPro has been done. I'm not sure that sending data via Vivado has been done. Here is a related thread. If this does not address your concern and if you don't find any other helpful posts on the forum, please start a new thread specifically for the DAC so the proper people can address.

Thanks, Josh