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DAC38j84

I'd like to use this DAC as a straight ahead DAC. I've not used a dac of this type before so I'm looking to see if it will fit our application.

First, I assume that we can turn all the filters off, and that we'll need to.

Stuff I didn't see on the data sheet but need to know:

1) What is the settling error at 3.3 and 6.7ns? I see it's 0.1% at 10ns.

2) How tightly are the 4 outputs matched? Is there any way to gain (or offset) match them?

3) We would want to be able to drive the output as a square wave at lower frequencies. Any problems with that usage?

4) We'd terminate the output with a 50 ohm resistor and drive that output into a high speed op-amp with a 10x gain. Any concerns with that?

5) Output compliance is listed a -0.5 to +0.6 V. With a 20mA output into 50 ohms, that means a 1V swing. It seems that this device is intended for use with a transformer. If we were to drive our op-amp in a single-ended fashion, we could only get 0.5V out of one output, yes?

Thanks!

Wally

  • Wally,

    I will look into this and get back to you.

    -Kang

  • Hi Wally,

    Regarding your questions:

    1a.All the FIR filters may be disabled except FIR0. This is basically 1x interpolation mode. 

    1b. I think the settling error may depend on external driving load and capacitance. I will need to find out more about this particular measurement and get back to you.  

    2. The 4 DAC outputs are designed to be delay and phase matched. There are coarse delays (adjust up to 3 DACCLK cycle) and fine delay (using custom FIR filters or group delay adjustment functionality). 

    3. Square wave at low frequencies should not be an issue. I think another way to spec "good" square wave is the rise/fall time. This again would depend on the load (and also measurement equipment load)

    4.No concern for 50ohm to ground. The DAC DC bias should be set at 0.3V for good symmetrical swing between 0V to 0.6V (max compliance). Therefore, the max full-scale current that can be set is 6.5mA. This gives an AC swing of 3.25mA and DC equivalent flow of 3.25mA. There is another 2.75mA of constant bias current per leg, so the total DC equivalent is 6mA. With 50ohm load and 6mA DC, the DAC will be sitting at 0.3V mid-scale. 

    5. If your amplifier does not have input common mode that can go below negative or means for negative rail bias, then the DAC output swing (per leg) will be limited to 0V to 0.6V. The compliance voltage range of the DAC is specified per leg. As long as the external bias network allows for negative swing, then the DAC output can output negative swing. 

    see attached app note for some interface ideas.

  • Regarding #1, the settling error is from simulation result. Since settling time would be load dependent, we recommend testing the settling time on our DAC EVM with the actual load attached to the DAC output.