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Hi.

Other Parts Discussed in Thread: ADS4249EVM

Hi, I am posting to ask for helps.

Now, I have tried to use TR4(FPGA board) with "ADS4249EVM" through "HSMC-ADC-BRIDIGE REV C".

But, I can not do that; can net get sampling clock.

So, if there is an manual for programming Verilog HDL or basic source code, please send me one.

Thanks and Best Regards,

Changhoon.

  • ChangHoon,

    Verify that you are getting an output clock at either J8 pins 56/58 or RN8 pins 3/4 of the ADS4249EVM. If this is not present, double check that there is at least a 0.8V p-p input clock at J19. Are you operating the EVM SPI interface in parallel mode or serial mode? There is no Verilog HDL code for this EVM. If you are referring to the  FPGA board, you will have to contact Terasic.

    Regards,

    Jim  

  • Jim,

    Thanks for your reply.

    I have checked and no matters at pins.

    I am operating the EVM SPI interface in parallel mode.

    Did Terasic cooperate for EVM and bridge board with TI?

    Thanks and Best Regards,

    Changhoon.

  • Changhoon,

    To my knowledge, TI did not work with Terasic on the bridge board. I did not understand your first comment about "no matters at pins". Does this mean there was no output clock at the pins? Without a clock, the FPGA is not going to capture any valid data.

    Regards,

    Jim  

  • Jim,
    There was no output clock at 56, 58 pins.

    Regards,
    Changhoon.
  • ChangHoon,

    On my ADS4249EVM, after I connect a 100MHz, 5dBm clock source to J19, I get an output clock and data after power up. Please send me the jumper settings on your board and I will compare them to mine.

    Regards,

    Jim

  • Jim,
    You mean that I can get an output clock and data after power up at any time? in situation when no connection with FPGA board is?

    If I use parallel, do I need to input any digital signal to ADC board?

    Thanks and Best Regards,
    Changhoon