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DAC37J82 Synchronization

Other Parts Discussed in Thread: DAC37J82

On page 107 of the specification for the DAC37J82(May 2014)  is a procedure for initializing. In general it states that once the DAC is set up, a SYSREF must be generated. In response, the DAC sets Sync_n low to begin the CGS alignment.

1) Based on this procedure, it appears that the synchronization process must be initiated by applying SYSREF to the DAC:  the DAC cannot initiate the synchronization (ie assert sync_n) autonomously. Is this the case, or is there a way that once the DAC is set up it automatically asserts sync_n?  

 2) What is the process for re-synchronization in the case when the DAC initiates the re-sync? Does the DAC automatically reset itself and generate Sync_n = 0, or is some external intervention required before the DAC can assert Sync_n?

  • Paul,

    1. The SYSREF (system reference) is needed to align the internal local multi-frame clock (LMFC) of the JESD204B logic of the DAC37J82. Upon the detection of the SYSREF edge, the LMFC will be aligned with the SYSREF so the logic is synchronized with the system. The JESD204B logic will also pull SYNCB low to request hand shaking protocol from the JESD204B transmitter (i.e. FPGA). This is the standard procedure for JESD204B subclass 1 operation.

    The device could potentially be configured without using SYSREF. Since the internal LMFC may not be aligned with the SYSREF, the latency across the JESD204B logic may vary and not deterministic. We do not recommend such operation.

    2. The DAC will automatically pull SYNCB low upon the loss of JESD204B link. This will request the JESD204B transmitter to start the hand-shaking protocol again to re-establish the link.

    -Kang