DAC39J84 questions

Mark Elkin

Other Parts Discussed in Thread: DAC39J84

FYI, I am the FPGA & software guy on a team at work that is designing a board with the DAC39J84 device. I was also appointed to be the POC within this team for the TI E2E forums.

We have some questions about the DAC39J84. We are planning to connect and use all 8 JESD204 (SERDES) lanes and all 4 internal DACs.

Can the DAC use "clock recovery" for timing of the SERDES data signals? Or is the SERDES clock solely based on the DACCLK and PLL(s)? If the latter, how much lane-to-lane timing offset (i.e. propagation delay differences) and jitter can it handle?

The data sheet provides the SYSREF setup and hold time requirements in the TYP (typical) column. Normally, requirements are given as minimum and/or maximum values. What does this TYP value represent? What are the consequences if we do not meet this value?

Is there a maximum duration (for example, N clocks) for the SYSREF signal? The FPGA core we plan to use requires SYSREF to be at least 4 clock periods long.

The data sheet says that SYSREF "is used for JESD204B Subclass 1 deterministic latency and multiple DAC synchronization". Is SYSREF needed for both the internal 4 DACs and external (chip-to-chip) synchronization, or only for external synchronization?

The data sheet says that the SYSREF buffer can be powered off. It also says the SYSREF input can be ignored. Is there some other method to synchronize the internal circuit blocks (PLL, NCO, etc) besides the SYSREF input? (Perhaps a command register bit accessed from the SPI interface?)

Regarding the local multi-frame clock, what is the relationship to this clock and the DACCLK and/or the SERDES clock? I do understand that the multi-frame interval will be based on the LMFS and HD settings. So, in other terms, how many LMFC cycles occur during a multi-frame interval?

Thanks,
Mark

over 7 years ago

0 Neeraj Gill over 7 years ago

TI__Mastermind 20541 points

Hi Mark,

We are looking into this, will respond as soon as we can.

Regards,
Neeraj Gill

0 Mark Elkin over 7 years ago

Prodigy 170 points

Thanks Neeraj,

Some of the questions above can be answered by the JESD204B spec if the chip's JESD204B engine fully complies with the spec. For example:

The lane-to-lane timing deltas (called "skew" in the spec) would be handled by the "RX Elastic Buffers", as long as each RX lane has a CDR that can determine its ideal sampling time in the digital signal's eye. The data sheet mentions a CDR, but without details of its operation and capabilities.
SYSREF set-up and hold times in the spec (and in typical digital signal systems) are minimums. So does TYP in the data sheet imply that the "minimum" values are the statistical mode, median or mean from a sample of these chips? If so, what is the range or standard deviation?
The LMFC will have a period that is an integer multiple of the DACCLK period, which itself should be an integer multiple period of the SERDES clock.

Is the chip fully compliant with the JESD204B spec?

There is just a single register, Config 61, for controlling the CDR and the SerDes Equalizer. So the selected config settings would apply to all lanes, right?
Even so, is there an individual CDR circuit for each RX lane? Is there a SerDes Equalizer for each lane? If not individual per lane, what are the lane-to-lane matching requirements?

The data sheet mentions the "elastic buffers". The allowed length appears to be [0...31], based on a config register field for choosing the length. It also says that the length must be <= k_m1.

Thanks,
Mark

0 Neeraj Gill over 7 years ago in reply to Mark Elkin

TI__Mastermind 20541 points

Hi Mark,

DAC39J84 is JESD204B subclass 1 device.

Yes selected config settings would apply to all the active lanes.
Yes each lane has its individual CDR circuit. SerDes Equalizer will also be applied to all the active lanes.
Yes elastic buffer should be <= K - 1 where K is # of frames per multiframe.

Regards,
Neeraj Gill

0 Mark Elkin over 7 years ago in reply to Neeraj Gill

Prodigy 170 points

Thanks Neeraj. That answers the CRD, skew, SERDES RX equalization, and elastic buffer questions. And the spec essentially answered the LMFC question. So just a couple questions remain...

0 Neeraj Gill over 7 years ago in reply to Mark Elkin

TI__Mastermind 20541 points

Hi Mark,

Can you please specify which question do you want answered?

Regards,

Neeraj Gill

0 Mark Elkin over 7 years ago in reply to Neeraj Gill

Prodigy 170 points

>> The data sheet provides the SYSREF setup and hold time requirements in the TYP (typical) column. Normally, requirements are given as minimum and/or maximum values. What does this TYP value represent?
-- In digital designs, SETUP and HOLD are always minimum required values. So is the data sheet saying that TI (statistically) measured the SETUP and HOLD for a sample of these chips, and that the typical value of these measurements is what is presented? Was the TYP value the statistical MODE, MEDIAN, MEAN, or some other value?
-- Also, what is the worst case value across the sampling? And therefore, shouldn't we be designing for the worst case so that every usage will work reliably?

If so, then...
>> What are the consequences if we do not meet this (TYP) value?

>> The FPGA core we plan to use requires SYSREF to be at least 4 clock periods long. Is there a maximum duration (for example, N clocks) for the SYSREF signal?
-- to clarify slightly...
For a PERIODIC signal, can we use a 50% duty cycle?
For a ONE-SHOT or GAPPED signal, is there a maximum number of clock cycles that the signal can remain asserted?

>> Is SYSREF needed for both the internal 4 DACs and external (chip-to-chip) synchronization, or only for external synchronization?

>> Is there some other method to synchronize the internal circuit blocks (PLL, NCO, etc) besides the SYSREF input? (Perhaps a command register bit accessed from the SPI interface?)

Thanks,
Mark

0 Neeraj Gill over 7 years ago in reply to Mark Elkin

TI__Mastermind 20541 points

Hi Mark,

I think you should use the sysref timing parameters as minimum value.

No there is no maximum duration limit for sysref signal. But we recommend to turn off the sysref after the DAC has established the link since it is divided down version of DCLK and may couple and cause spur at the DACs output.

Yes sysref is need for both internal and external synchronization.

You can synchronize internal circuits using SIF sync.

Regards,

Neeraj Gill

0 Mark Elkin over 7 years ago in reply to Neeraj Gill

Prodigy 170 points

Thank you. Once our board is built, I will check back in on this and let you know how it went. (Will be 2-3 months.)

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