Question about ADC12J1600EVM and TSW14J56

Hi Jim,

Thanks a lot for the attention. I didn't understand only the part of the frequency limitation. I'll acquire signals around 200 MHz bandwidth. How could I solve this? Will the solution result in some penalty?

Thanks and best regards,

Hi Carolina

With your relatively low frequency input I recommend you reconfigure the ADC12J1600EVM for differential DC-coupled inputs. Here are instructions on how to do that: https://e2e.ti.com/support/data_converters/high_speed_data_converters/f/68/p/484862/1755968#1755968

Then also acquire one of these balun boards:http://www.ti.com/tool/adc-wb-bb. The differential outputs of the balun board will connect to the differential inputs of the ADC12J1600EVM. That combination will give you a frequency range from 4.5 MHz to 3 GHz.

If you need to have coverage all the way down to DC then you can use an amplifier evaluation board to perform Single-Ended to Differential conversion. Something like this should work:

http://www.ti.com/tool/lmh6554le-eval

http://www.ti.com/product/LMH6554

When using a DC-coupled amplifier evaluation board you will need to ensure you use the ADC12J1600EVM Vcmo (common mode voltage output) to set the Vocm or Vcm (common mode voltage input) of the amplifier EVM.

Best regards,

Jim B

Thank you very much, Jim

This frequency range will be more than enough. I will need to use it as single input only, so I suppose I'll be able to store 2 GSa of data from one channel, right?

Have a nice day.

Carolina

Hi Carolina

Yes, you will be able to store 2 Gsamples of 12 bit data from this ADC EVM.

Best regards,

Jim B

Thanks, Jim!

We'll buy the FPGA, but regarding the ADC, perhaps 1 GSa/s is too much for us. We are considering this one instead: http://www.ti.com/tool/ADS54J66EVM

Does it run 500 MSa/s in each one of the four inputs? Do I need any modification to cover the whole bandwidth, from a few megaherz to 900 MHz?

Thanks and best regards,

Carolina,

The ADS54J66 will sample all four inputs at 500 Msps. What mode do you plan on using for this part? If you use dec 2x or dec 4x you will have to write to registers when the input signal falls out of the bandwidth of the decimation filter selected.

Regards,

Jim

Thank you, Jim

I intend to use it to receive signals with bandwidth around 100 MHz to 800 MHz.

Best regards,

But I don't know about the decimation, what matters to me is just to acquire the data in the proper bandwidth. Does it change anything?

Thanks, Jim!

I intend to use it to acquire real data. The spur frequency won't be a problem if I know it is there, so I can ignore it after processing the data.

Best regards,

Hello Jim,

Thanks for all your help. The application is to use as a receiver for optical sensors in research applications. We've bought the ADC+FPGA and it shall arrive this week. I appreciate all your help.

Best regards,

Hi Carolina

Regarding your questions above:

• The ADC12J1600EVM and TSW14J56EVM Rev D combination can store up to 2G raw 12-bit ADC samples.
• Yes, the EVM can be configured for operation at 1GSa/s.
• The default configuration of the ADC12J1600EVM gives an input bandwidth of approximately 400 MHz to 3 GHz.
  The EVM can be reconfigured for differential DC or AC-coupled inputs. In those configurations the lower frequency limit will be determined by the differential driver. The high frequency limit will be the lower of 3 GHz or the driving circuits maximum frequency.

Let us know if you need anything else.

Best regards,

Jim B