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ADS54J60 Initial Lane Alignment

John Gasco
Prodigy 30 points
Other Parts Discussed in Thread: ADS54J60

I'm trying to bring up a Virtex-7 GTX receiver interface to the ADS54J60 and I cannot see the expected K28.5 comma characters used for code group synchronization on the receiving end when the ~SYNC signal is driven low from the FPGA to the ADC. I've also tried using the other test pattern modes available in the ADS54J60 (register 2h, JESD digital page 6900h, bits 7:5) but these also don't seem to show up on the received data. The deserialized data I'm getting appears to be random and non-repeating. I'm trying to use LMFS=4211 with 2 lanes per ADC running at 10Gbps. Here is the pseudo code implementation for my initialization sequence:

<Pulse physical reset pins>
write_register(0x0-000, 0x81);
write_register(0x0-011, 0x80);
write_register(0x0-059, 0x20);
write_register(0x4-003, 0x00);
write_register(0x4-004, 0x68);
write_register(0x6-0F7, 0x01);
write_register(0x6-000, 0x01);
write_register(0x6-000, 0x00);
write_register(0x4-003, 0x00);
write_register(0x4-004, 0x6A);
write_register(0x6-016, 0x02);
write_register(0x4-003, 0x00);
write_register(0x4-004, 0x69);
write_register(0x6-001, 0x02);
write_register(0x6-007, 0x08);
write_register(0x6-000, 0x80);
write_register(0x6-006, 0x1F);

Am I missing some important register write to make these settings take effect or might there be something wrong with the actual settings being written? I would expect something like a repeating K28.5 character to show up on the receiving end as long as there aren't any significant SI issues and the ADS54J60 transmitter is correctly configured for 10Gbps...

Thanks!

  • 0
    TI__Guru* 91947 points

    John,

    Register add 0x01 on page 6900 needs to have a 0x04 written to it, not 0x02 for 4211 mode. Also, are you providing both a reference and core clock to the Xilinx FPGA?

    Regards,

    Jim

  • 0 in reply to jim s
    Prodigy 30 points
    Jim,

    Thanks for the response. I tried setting register address 0x01 on page 6900 to 0x04 instead of 0x02, but I'm still not able to see the K28.5 cahracter. The Xiling FPGA does have both a reference clock and a core clock. I'm able to verify that the PLLs for the Xilinx transceivers are locked, and I'm also able to successfully establish a JESD204B link between the transmitters in these same transceivers and a DAC on the same board so I'm relatively comfortable saying that the clocking for the FPGA side is working correctly.

    Thanks,
    John
  • 0 in reply to John Gasco
    TI__Guru* 91947 points

    John,

    If the link was established, you had to have received 4 consecutive K28.5 characters. I am not sure what your issue is. Is SYNC being de-asserted by the FPGA?

    Regards,

    Jim

  • 0 in reply to jim s
    Prodigy 30 points
    Jim,

    My issue was that the link to the ADS54J60 was never established because I wasn't receiving 4 consecutive K28.5 characters. The link that I mentioned being able to establish in my previous post was to a DAC on the same board using the transmitters in the FPGA, and the only reason I mentioned that was to explain my reasoning for having confidence in the clocking within the FPGA. The SYNC signal to the ADS54J60 is being de-asserted by the FPGA.

    I was able to resolve the issue where I wasn't seeing the K28.5 characters. The issue was that my SYSREF signal was disabled going to the ADS54J60 while I was going through the initialization sequence that I listed in my original post. By turning on SYSREF before running the initialization sequence, it seems as though this allowed all of my register settings to take effect.

    Thanks,
    John