Hello
I'm Alber as a FAE in Arrow Korea
My customer are testing the ADS54J42.
They have 2 questions about ADC architecture.
1. coefficient values of each filter in DDC block(LPF, HPF, BPF, IQ LPF)
- Would you please let me know each coefficient values in detail?
2. can they use following setting?
- FPGA input Sampling Rate : 300Msps(Real)
- DDC Mode in ADC : Bypass
- JESD204B LANE use : 2 Lane(1Lane/Channel)
- There's no use case on datasheet using both DDC bypass mode and 2Lane.
- Only 2 Lane connected between ADS54J42 and FPGA on their board now.
- They want to receive whole 150MHz BW without any BW rejection for DPD function(3x BW of 50MHz signal BW)
(Feedback center Frequency is fixed at 225MHz)
- If possible, what frequency have to take in the clock input port?, and would you please let me know how to set the ADC's register?
Please, they are ungent now, I look forward to get a feedback quickly.