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ADS54J42 Filter Coefficient & other JESD204B Usecase

Other Parts Discussed in Thread: ADS54J42

Hello
I'm Alber as a FAE in Arrow Korea
My customer are testing the ADS54J42.
They have 2 questions about ADC architecture.

1. coefficient values of each filter in DDC block(LPF, HPF, BPF, IQ LPF)
  - Would you please let me know each coefficient values in detail?

2. can they use following setting?
  - FPGA input Sampling Rate : 300Msps(Real)
  - DDC Mode in ADC : Bypass
  - JESD204B LANE use : 2 Lane(1Lane/Channel)
 
  - There's no use case on datasheet using both DDC bypass mode and 2Lane.
  - Only 2 Lane connected between ADS54J42 and FPGA on their board now.
  - They want to receive whole 150MHz BW without any BW rejection for DPD function(3x BW of 50MHz signal BW)
    (Feedback center Frequency is fixed at 225MHz)
  - If possible, what frequency have to take in the clock input port?, and would you please let me know how to set the ADC's register?


Please, they are ungent now, I look forward to get a feedback quickly.

  • Alber,

    I am working on getting you the answer to these ASAP.

    Regards,

    Jim

  • Hi, Jim

    Would you please give a feedback whether use available or not?

    If not, they have to change the whole architecture (clocking, sampling rate, IF CF and so on)...

    As I mentioned, they are very urgent to get a TI's feedback.

    And if you have any question about this issue, please ask me anytime.

    Thanks.

  • Alber,

    We can only share filter response. Revealing filter coefficients may not be possible since we would need to explain filter architecture in that case.
    Why does customer need the coefficients?

    I am still waiting on answers from the design team regarding the other question.

    Regards,

    Jim 

  • hi, Jim

    I understand that you can't share the filter coefficient due to asking other questions from customer.

    They just want to double-check the filter response in detail.

    I will say that this situation to customer.

    Anyway, they need to get the TI's feedback whether using the configuration setting available or not .

    Please get the answer quickly from design team.

    Early I mentioned, they are very urgent.