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ADC32RF45 4221 config file.

Other Parts Discussed in Thread: ADC32RF45EVM, ADC32RF45, ADC32RF80, LMK04828, LMX2582

I'm trying to use 4 JESD lanes to capture baseband DDC IQ data at (decimate x4)  614.4MHz with a sample clock of 2457.6 MHz using the ADC32RF45evm board.

To make this sort of work, I load up the clock file LMK_ADC32RF45_lmfs82820_2457p6_MSPS.cfg and my own custom setup file that sets the decimation to 4 and the NCO frequency to 780 MHz (My input signal is a 500MHz wide set of tones centered at 780 MHz).  

The final trick was to use the ADC32RF80_LMF_8221 configuration in HSDCP.  Unfortunately this is using 8 lanes at 6.14Gb/s and I want to use 4 lanes at 12.28 Gb/s.  Are there more config files for HSDCP somewhere that will allow me to do this?  I also assume that I will need to do some JESD configuration in the ADC32RFxx EVM to set this up as well, so any insights there would be helpful also.

  • Hi,

    we have been working on adding more and more configuration files to the GUI for all the different modes of operation.  I just looked at what I have so far and the 4x decimation complex is not one of them yet.  But I can go create that one and verify it.   In the configuration files folder there is a subfolder for pre-production silicon that had many modes ready and I am getting these same modes ready as time allows for the final silicon.   The pre-production files are not usable for the final EVM, but it is pretty easy to go through and make all these new config files.  I generally take a verified config file such as the ADC32RF4x_DDC_8xIQ_8821.cfg and with the datasheet in hand I change the settings for PLLMODE, JESD MODE0, JESD MODE1, JESD MODE2, DECIM FACTOR, and if needed the 40x MODE to match what the datasheet calls out for the mode I want.   Oh, and the config file also sets the divider ratio for the LMK so that I can decouple the rest of the LMK programming from the ADC programming, and just have LMK config files for external clock or different frequencies, and not also have to have LMK files for all the different decimation factors.   That way I can just load an LMK config file, then an LMX config file if needed, and then the ADC file for my mode.

    I'll check out the decimation by 4 complex case and post the config files that I come up with.  But in the meantime you could also try your hand at it too if you want.   There is a handy way to keep straight the address and data edits needed for the config file.  if you double click on the lower left window of the SPI GUI where you see the address/data operations quickly scroll by as you load something, then a log window pops up.  I right-click to clear the log window.  Then I use the GUI to click on the settings I need for PLL MODE and the others, getting from one mode to the desired mode, and then the log window shows me exactly what the address/data pairs are that I need to edit in the config file.  So if I edit PLL MODE and there is another bit already set in that register then I don't risk losing track of that bit when I go to set the bit I want.

    Regards,

    Richard P.

  • Thanks for the response.  However, I'm missing something I think.  I need to be able to set the mode in HSDCP to something like ACD32RF45_LMF_4421 so that it uploads new firmware to the FPGA to use only 4 lanes and sets the rate to twice what it was for the 8 lane case.  I'm not sure of the linkage between the HSDCP and the ADC gui.  In fact, to make the 8 lane complex case work I used the ADC32RF80_LMF_8221 case from the pulldown in HSDCP.  

    What I do is this:

    Steps to bring up ADC board:

    1)      Hit reset on LMK04828 panel

    2)      Load from low level view: C:\Program Files (x86)\Texas Instruments\ADC32RFxx EVM_revD GUI\Configuration Files\PreProduction Silicon\ADC32RF45 bypass DDC\LMK_ADC32RF45_lmfs82820_2457p6_MSPS.cfg

    3)      Hit ADC reset button

    4)      Load Configuration file is here: V:\CD\EIE\projects\Cryo_Sensor\ADC32RF45eval board\ADC_setup_8lanes_DDC.cfg (my own custom config)

    5)      Run HSDCP and set ADC output rate to 614.4M and load up the ADC32RF80_LMF_8221 ADC setup.

    I thinks it's step 5 where I need the change, I guess I can try using the ADC32RF40_LMF_4421 ADC setup and then futz around with the JESD stuff on the ADC gui to set the config up for 4 lanes...  

    Thanks for your help!

    Dan

  • Hi,
    Your HSDCPro should already have the device selections for the LMFS_4421. What revision of HSDCPro are you using? You should see a device selection with the name ADC32RF80_LMF_4421. Perhaps that is the confusing part - the ADC32RF80 is just an ADC32RF45 that only supports the DDC functions, so by using the RF45 in decimate by 4 mode it is the same as an RF80 in decimate by 4 mode. The ADC32RF80_LMF_4421.ini file tells the HSDCPro where to find the bits for each sample on each lane, and as you can see in the datasheet that the lane mappings are different between LMFS8821 and LMFS4421, so the ini file that is there for the LMFS8821 device selection and the LMFS4421 device selection will give the HSDCPro different instructions on where the find the bits on which lanes. So the HSDCPro side of things is already done for you, and if it wasn't we wouldn't expect you to have to sort it out - it is something we provide.

    I presume you have a recent EVM, and not pre-production silicon. I haven't migrated all of the LMK configuration files from the pre-production folder of config files yet, just the ones for external clocking. But for the LMK clocking you went to the right place to find an appropriate LMK config file. But not the LMFS_82820 file. There is one called LMK_ADC32RF80_2457MSPS.cfg that you should use. You are editing the divider ratios anyway to be what you need, but the SYSREF divider is different between the LMFS_82820 mode and the decimation modes.

    Then when I check out a config file for the decimate by 4 mode that you want, the file name of the config file will indicate the LMFS for that configuration and you would just choose the HSDCPro device selection that matches that LMFS. (treating RF80 and RF45 as the 'same' thing for the moment. ) I hope to create that config file and post it tomorrow morning.

    Regards,
    Richard P.
  • Still looking for a solution here. In poking around, I've noticed one major thing with the ADC32RF45 GUI that need to be fixed. When loading a configuration from the low level view, the registers do not seem to be back populated to the other tabs. To reproduce this, do the following:
    1)Set the HSDCP to ADC32RF45_LMF_8224 with a data rate of 2.4576G (You should have previously set this on the ADC cards clock).
    2) Go into the DDC configuration and set the ChA DDC EN to enabled
    3) Then load up the low level config called: ADC32RF4x_14bit_LMFS_8224.cfg
    4) When you go back to the DDC configuration, you will see that the ChA DDC EN is still enabled. However, you will be able to get data just fine.
    Un-check the DDC enable and you will set you still get data. Now, check it again, and you will see that the HSDCP hangs. Go back and uncheck it and you will get data again. When you loaded up the config, good software practice says that you should also back-fill the other parts of the GUI with the values you just loaded up. Your other device GUIs do this, so should this one.

    Anyway, back to the problem I am trying to solve. I want to configure the ADC32RF45 to run in 20X mode LMFS4221 as listed in table 17 in the ADC32RF45 datasheet. I believe this will need some sort of configuration change to the HSDCP configuration because if you look in table 17, you will see there are two setups for LMFS4421 (20X and 40X). They use differing lanes, and as a consequence, the mapping in the HSDCP will need to be different (I think). In fact, it looks like to used divide-by-4 decimation, I will need to use the 40X mode because table 16 does not show that it's possible to use the 4421 mode with 20X for single band complex output.

    I'm still trying to solve this by changing configs, but it's very confusing especially when loading configs does not back fill the GUI.

    Regards,
    Dan
  • Hi,

    I will be checking out this configuration this afternoon.   I set it up the way I thought I wanted it last Friday but ran into trouble and will have another go at it this afternoon.

    Yes, there are cases where there are two different modes of operation where one mode would use lanes 0,1 while the other mode would use lanes 1,2.  In these cases, there are separate ini files for the HSDCPro for each case.  Usually one of the modes would use the ADC32RF45 PLL MODE as 40x while the other mode would be 20x, and the name of the ini file would include the text _40x_ or _20_ in the file name to distinguish the two, and the name of the ADC config file itself would also contain the same text string so that the ADC config file and HSDCPro ini file could be matched up properly.

    And looking at the ini files that come with HSDCPro is see a device selection for ADC32RF80_20x_LMF_4421.ini and another for ADC32RF80_40x_LMF_4421.ini.  The one we would use would in fact be ADC32RF80_40x_LMF_4421.ini.

    Regarding the back-annotation from loading the config file to seeing the correct settings show up on the GUI tab, that is why the User Guide for the EVM contains the step 'READ ALL' after loading the config file.  "Press Read All on the low level tab. (The settings loaded by the ADC config file in step 7 will not be reflected in the ADC32RFxx main tab unless the ‘Read All’ is performed.)"  There is a reason for this, and this should be addressed by the time the silicon releases to production and the SPI GUI is revised one last time to account for everything.   You'll notice in the datasheet that there are a number of different blocks of SPI registers with different rules for the use of each section.   Some use pages x4003 and x4004.  Others use pages x0011 or x0012.  Some use bit 12 of the address to select the channel.  others don't.   The SPI GUI has 'block' definitions for each of these register spaces, and the block definition includes setting page addresses.  But if you open the config file with Wordpad or similar you will see that I skipped using those block definitions and used a block called 'lowlevel' for everything and I have to manually keep track of page addresses.  This use of 'lowlevel' breaks the back-annotation from the config file back to the main tab controls.   But clicking 'READ ALL' makes the GUI read all registers and then set the tab controls to match what was read.    On pre-production silicon while there were so many 'special' registers being set and not all other registers yet documented in the datasheet the use of the lowlevel block was necessary.  Eventually we will edit these config files to edit out the use of the lowlevel block for any registers that have a control on one of the tabs.

    Regards,
    Richard P.

  • Hi,
    I got the decimation by 4 mode, single band LMFS_4421 working yesterday, but I had to switch to a different lab bench. Something had failed on my usual lab bench and I haven't isolated the problem yet. But as I debug it between the two benches, I will encapsulate the setup for your mode into a new config file and post that later today. I just had to follow the steps I had outlined for what I usually do in developing a new config file - I brought up a baseline setup such as decimation by 8 complex dual band, and then with datasheet in hand go to the ADC tab and change the controls from the base line mode to the new mode. In this case, I had to edit JESD MODE0 to 0, JESD MODE2 to 1, PLL MODE to 40x, 40x MODE to 111, click for single band, change to 4x interpolation. And do the same for channel B. Channel A and B cannot be set for different modes of operation. And then change the LMK04828 clock divider for the FPGA from 16 to 8. I think that was all, and choose the correct device selection in HSDCPro and enter the right sample rate after accounting for decimation.

    Regards,
    Richard P.
  • Hi,

    please see attached for the configuration file. 

    HSDCPro device selection to match this config file would be ADC32RF80_40x_LMF_4421.  I used external clocking on the lab bench, but if you are using the LMK04828 or the LMX2582 for clocking that is ok because the last thing the ADC config file does is set the divider ratio in the LMK to the proper value (div by 8) for the 4x decimation case.  I spent a little extra time comparing the configuration to previous cases because I was missing 6dB of signal amplitude in the resulting FFT, and found that we normally set the 6dB GAIN setting for the DDC, but not the wideband 6dB GAIN setting and when in 4x decimation the usual 6dB GAIN checkbox I had been using no longer was applicable, and to keep it apples-to-apples I had to also set the WBF 6dB GAIN checkbox.  But that is described in the datasheet, that when using 4x decimation it is the wideband path of the DDC that applies.

    Regards,

    Richard P.

    ADC32RF4x_DDC_4xIQ_4421.cfg