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DAC37J82 register pll_cp_adj

Andre de Buren
Prodigy 20 points
Other Parts Discussed in Thread: DAC37J82

Is there any formula or to calculate the optimum charge-punp current in function of the P Pre-Scale and M dividers?

The data sheet mentions in Chap. 7.4.1 only an optimum of 600 uA for P- and M-ratio of 2 and 4 but I need P = 10 and M = 4.

  • 0
    TI__Guru 65954 points
    Hi Andre,

    Right now the best method to observe the phase noise spectrum vs charge pump. I may need to ask around to see if there are existing formulas available from design team.
    I was able to perform the following experiments to verify the optimal charge pump for best overall phase noise and frequency peaks. You may do so with a Agilent E5052 phase noise analyzer and NCO options on the DAC37j82. Empirical data is always better than formulas, in my opinion.

    e2e.ti.com/.../446642

    -Kang
  • 0 in reply to Kang Hsia
    Prodigy 20 points

    Hi Kang,

    Thank your valuable answer.

    The best would be a calculation followed by a measurement  and fine tuning.

    André

  • 0 in reply to Andre de Buren
    TI__Guru 65954 points
    Hello Andre,

    Here are some guidelines from designer regarding charge pump setting:
    " The 5-bit pll_cp_adj<4:0> is to set the charge pump current in a linear scale. Pll_cp_adj<4:0> =00001 gives 50uA, 00010 for 100uA while 11111 gives 1.55mA. In nominal condition, if vco runs at 5GHz with P-ratio and M-ratio set as 2 and 4, the dacclk frequency would be 2.5GHz and PFD frequency 625MHz. This needs pll_cp_adj<4:0> equal to 01100 which give 600uA charge pump current to stabilize the loop and gives the optimized phase noise performance. When “P-ratio times M-ratio”(P*M) needs to be increased, the charge pump current needs to be increased to sustain enough phase margin for the loop. On the other hand, the charge pump current needs to decrease when P*M decreases.

    With P=2 and M=4, the charge pump current can be set to 300uA (00110) to guarantee the PLL loop has a
    close to or larger than 60 degree phase margin. With P=2 and M=8, the charge pump current can be set to 500uA (01010) to guarantee the PLL loop has a close to or larger than 60 degree phase margin. However, the phase margin can be lowered to 55 degree or even lower value by increasing the charge pump current to get optimum phase noise performance out of the loop."

    In some situation the system needs a very slow pfd frequency. For example, with the scan clock 10MHz the feedback dividing ratio (P*M) needs to be 400 if the VCO runs at 4GHz. Since the loop gain is so small with the dividing ratio, the charge pump current needs to be increased to maximum to help stabilize the loop. With maximum current 1.55mA, the phase margin is still too low with merely an internal loop filter. So an external loop filter can be connected to the pin pll_lf_in to make the pll loop phase margin around 65 degree. The recommended value are R1=300 ohm, C1=100nF, C2=1nF as shown on the datasheet.

    For the specific use cases, it is best to follow-up with empirical measurement.

    -Kang