how to conncet ads54j60 / tsw14j10 /kc705

Weibo,

Sine the KC705 only has four RX lanes routed on the FMC connector, we did not generate ini files for the ADS54J60, as only channel B could be used. We do have ini files for the VC707, which routed 10 RX lanes and can be used for both channels. These can be found in the directory as shown below. If you need only channel B of the ADS54J60, we could generate an ini file for you.

Regards,

Jim 

 

thanks your reply, we also have Xilinx kcu105 , can you provide me the ini file used for kcu105. meanwhile, i also be glad to receive an 4 lane ini file for kc7050. once again,i use the board ads54j60 not tsw54j60

and i want to know, if i have the right ini file for hsdc software, can you provide me the cfg file for the ads54j60 debug software.

Weibo,

We are currently working on ini files for the KCU105. Due to this board not having a JTAG connector interface to the FPGA, the TSW14J10EVM will not work with this platform. For this setup, the user must load the FPGA using Vivado and then run HSDC Pro GUI across an Ethernet connection. We should have this firmware and instructions available in the next few weeks. What LMFS setting do you plan on using with the ADS54J60?

Regards,

Jim 

ok, i will wait a few weeks. now,can you provide me ini files for kc705, just four lanes will be ok. any lms will be ok, i want to learn and modify it to actual project. actuallly , recently weeks, i am trying hardly write my code in vivado for kcu105, but it failed. the FPGA can send a sync, can't receive valid adc data.
anyway, now, can your provide me related ini file and firmware for kc705.
thanks.

Hello, Jim

i'm waiting for your ini file  of  ads54j60  for kc705 .

thanks very much !

Weibo,

Since I could not locate a KC705, I had to test this ini on a VC707. I think it will work for the KC705 as well. Just copy the attached ini to the system file location indicated by the attached document then follow the remaining instructions. Please  remember to only use CHB of the ADC EVM as the KC705 did not route the lanes needed for CHA.

Regards,

Jim

KC705_CHB_LMF_4211_Fs_983p04M.pptxADS54J60_LMF_2211.ini

 

thankyou , i will try it tomorrow !

thanks againg , you give me a wonderful ppt and detail instrutions . And ,i have a quesion, you give me " ADS54J60_LMF_2211.ini " ,and use "ADS54J60_LMF_4211.cfg" to config ads54j60 register . did the "Lmf_2211" in accordance with “lmf_4211" ? the lane is 2 or 4？

thanks againg , you give me a wonderful ppt and detail instrutions . And ,i have a quesion, you give me " ADS54J60_LMF_2211.ini " ,and use "ADS54J60_LMF_4211.cfg" to config ads54j60 register . did the "Lmf_2211" in accordance with “lmf_4211" ? the lane is 2 or 4？

Weibo,

The ADS54J60 has both ADC's running but the KC705 is only capturing data from one. This why these files appear as they do. The ADC is driving 4 lanes but the KC705 is only capturing data on 2 lanes.

Regards,

Jim

Jim,
thank you , I can capteure data from kc705 use your ini file . although the signal is not very good sometimes .

Weibo,

Can you send a screen shot of the GUI when you get a bad capture? I would like to see if I can help with this issue.

Regards,

Jim

Hi Jim,

I tried same procedure, that is, KC705 + TSW14J10 + ADS54J60EVM.

But, I encountered "Time Out Error" and could not get any data.

"D3" of JESD_SYNC did not lighting on ADS54J60EVM.

Can you explain the details of setup procedure?

I bought TSW14J10 due to evaluate ADS54J60 purposely.

I'm disappointed.

Regards,

Kei

Jim,

Thanks for quick reply.
I already know PPT document and additional files.
But I encountered error that mentioned before.

I think this procedure is not completed.
Are you verify this procedure on KC705?
Some slide on ppt file showed VC707 for interface information.

Regards,
Kei

Kei,

It appears you are selecting the wrong device ini file in HSDC Pro from what I can tell from your screen shot above. You need to copy the ini file I sent yesterday to the directory called out in the start up guide. When you open HSDC Pro, if you copied the file to the correct location, you should be selecting the ini called "ADS54J60_LMF_2211". This is not what is  shown above.

Can you verify also that the status LED's 7, 6, and 5 on the KC705 are blinking after you loaded the FPGA firmware. I followed the start up guide just now with my setup and had no issues.

Regards,

Jim

Weibo,

The ADC will be operating in 4 lane mode but the FPGA will be in 2 lane mode.

Regards,

Jim

Jim,

Thanks for reply.

Here it is. Please check it.

Regards,

Kei

Kei,

After everything is loaded, is D2 on the ADC EVM On? For the KC705, are status LED's 7, 6, and 5 blinking and 3 and 1 On?

Regards,

Jim 

Jim,,

Please see my previous posted photo.

D2 on the ADC EVM is "ON".

KC705's LED 7, 6, and 5 are "binking" and 3 is "ON" and 1 is "OFF".

Regards,

Kei

Kei,

It appears that the boards are not achieving sync. Do you have a TSW14J56EVM to verify that the ADS54J60EVM is working properly?

If not, you can send us you ADC board and I can try testing it with our setup. If you do this, at the same time I can send you the board I am using. Just provide me with a shipping address and phone number.

Regards,

Jim

Jim,

Thanks for your support. I don't have a TSW14J56EVM.

But Ｉ'm in Tokyo, Japan.　Ｉ have to ｓｅｎｄ ADC board you by a foreign freight.

May I ship it by freight collect?

Regards,

Kei

Kei,

How did you order the original ADC board? Let's just work on getting you a replacement for now. If it was a distributor, they should be able to order a replacement and ship the bad one back at no cost to you.

Regards,

Jim

Jim,

Thanks.

I bought ADS54J60EVM from TI store.

I'll tell you my address as a private message. 

Regards,

Kei

LMF_2211 is 2 lanes and lmf_4211 is 4 lanes.

Hi Jim,

I got new board and I've been confirmed ADC captured data on my environment.

But it was very bad noise floor. Attached please check real codes.
This wave data was measured without signal input. So, correct code is around mid-code(32768).

A metastability error may be occurred.

If you have any idea to solve it, please let me know.

Regards,

Kei

Kei,

Did you follow the instructions in the attached document? Did you press the ADC board reset after loading the LMK config file but before loading the ADC config file? What is the available amount of current from the supply connected to the ADC EVM? Make sure this is at least 3A.

Regards,

Jim

5481.ADS54J60_KC705_CHB_LMF_4211_Fs_983p04M.pptx

Jim,

Thanks for your quick reply.

Digital reset asserted before loading ADC config file.

Captured data is better than before, but a metastability error may be still occurred.

Is there any recommendation setting for ADC config?

Regards,

Kei

Kei,

Try using this ADC config file. You may also want to try a slower sample rate to see if this helps. How old is your KC705 board? Do you know what speed grade FPGA it has?

Regards,

Jim

ADS54J60_LMF_8224_new.cfg

Jim,

Thank you for your kind support.

KC705 is rev1.2. Speed grade is -2 (XC7K325T-2FFG900C).

I tried some sampling frequency with the attached ADC config.

ADC function has been confirmed until 737.28Msps, however it couldn't work at 983.04Msps.

Attached please find FFT results.

Do you have any special means to work at around 1Gsps?

Regards,

KeiADS54J60_LMF_4211_new.cfg

Kei,

The board should work with no problems at 1GHz. Have you verified you have a valid input signal? It almost appears to have a modulated signal on top of it. What frequency is your source? Are you using a filter?

Regards,

Jim

Weibo,

The KC705 uses the .ini file, which had to be set to 2 lane mode as we are only capturing 2 lanes of information. The ADC is running in 4 lane mode as this was the easiest config file to create. The link is established since the FPGA is only monitoring the lanes from one ADC channel.

Regards,

Jim

Jim,

Input signal is provided from signal generator with low pass filter and no modulation.
It still cannot measure over 800MHz under our environment.

Is there any means to check ADS54J60 function like BIST?

Regards,
Kei

Kei,

Only PRBS. Is 800MHz your clock rate or IF input? Is the setup working at 800MHz and slower? What LMK config file are you loading?

Regards,

Jim

  

Jim,

800MHz is ADC clock (sampling rate).

I loaded the attached ini file as following your setup procedure.

LMK_Config_Onboard_983p04_MSPS.cfg

Sampling rate has been changed by DCLK divider setting as below.

VCO frequency	ADC Sampling freq.	CLKout0/1	CLKout2/3	CLKout12/13
2949.12MHz	983.04MHz	VCO/6	VCO/3	VCO/12
2457.76MHz	819.2MHz	VCO/6	VCO/3	VCO/12
3072MHz	768MHz	VCO/8	VCO/4	VCO/16
2949.12MHz	737.28MHz	VCO/8	VCO/4	VCO/16

Over 819.2MHz, captured data has been broken.

Regards,

Kei