DAC5681z output voltage swing

Ashwin Maurya

Other Parts Discussed in Thread: DAC5681Z, DAC5682Z

Hi ,

I am using DAC5681Z (DAC, 16-bit 1.0 GSPS) first time. our Analog output Voltage requirement is 0 to 2V. I am planning to use internal voltage reference of 1.2V.
I could see IOUTB1, IOUTB2 Compliance voltage can vary from AVDD–0.5 to AVDD+0.5. if AVDD=3.3 then Compliance voltage will be 3.8V to 2.8V.

So my Doubt is
1) By using 1:1 Balun, shall we get output is 3.8V to 2.8V or +0.5V to -0.5V?
2) Can i use any single transformer, which can directly provide 0 to 2V. If not please share opinion to get 0v to 2V output ?
3) Can we use any Opamp for same in range of 500Mhz output signal?

over 7 years ago

0 Neeraj Gill over 7 years ago

TI__Mastermind 20541 points

Hi Ashwin,

I am looking into this question. I will respond tomorrow.

Regards,

Neeraj Gill

0 Ashwin Maurya over 7 years ago in reply to Neeraj Gill

Prodigy 80 points

Thank you Neeraj.

looking for your valuable suggestion.

Regards

Ashwin

0 Neeraj Gill over 7 years ago in reply to Ashwin Maurya

TI__Mastermind 20541 points

Hi Ashwin,

1. Your output will be -0.5V to +0.5V. The bias 3.3 V dc is on dac output side of the transformer and does not pass through the transformer.
2. It might be possible but we haven't done something like this before. I think you will need a transformer with center tab on both the primary and secondary side( I don't know if there are transformer of this type). if you could bias the output such that output swing is only positive.
3. I think the best way would be to use the op amp. Here is the TI design that was done using DAC5682z which is the dual version of DAC5681z. www.ti.com/.../tsw3070evm

You can also read following document that explain how the outputs of DAC can be interfaced with OP amps.
www.ti.com/.../slaa399.pdf
www.ti.com/.../slyt342.pdf

Regards,
Neeraj Gill

0 Ashwin Maurya over 7 years ago in reply to Neeraj Gill

Prodigy 80 points

Hi ,

I am using DAC5681z. We are planning to use DAC in external clock mode. CLKIN / CLKINC (1Ghz) will be provided by a Clock translator ICs 8T49N287.

1) Is external clock possible without using VCXO?
2) What is max clock jitter allowed for thses pins to degrade output waveform.

0 Neeraj Gill over 7 years ago in reply to Ashwin Maurya

TI__Mastermind 20541 points

Hi Ashwin,

1. Yes.

2. The maximum jitter requirement will be set by the desired SNR at the output of the DAC. The phase noise and therefore, SNR of the DAC output tone is 20log10(Fdac/Fin) +3 dB better than the phase noise of input clock signal.

Regards,

Neeraj Gill

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DAC5681z output voltage swing