ads5400 evm interfacing with Xilinx Kc705

Adam,

We do not have firmware for this. As long as the signals map to valid pins on the FMC connector on the Xilinx board through the adapter, you should be able connect these together. There are resistors on the ADS5400EVM, that when installed/removed, would allow access to the SPI pins of the ADC through the I/O connector.   

Regards,

Jim

Jim,

Thank you for you response. Just for clarification, if I install resistors then this would give me access to the SPI pins and without them installed, as the board is currently, the SPI pins are not available. Are you referring to R18, R38, and R72? If so what would be appropriate resistor values? When I look at the User guide for the ADS5400EVM (slau 293) I see the the resistors are marked DNI and do not have a resistor value. Thank you for your help.

Adam

Adam,

Remove R54, R78, R82 and R86 to disconnect the USB interface to the SPI lines. Install 0 Ohm resistors at R18, R38 and R72. Since there are only three connections going to the ADC SPI from the connector, you will have to operate the SPI bus in 3 wire mode. The schematic is attached for your reference.

Regards,

Jim

  ADS5400EVM-SCH_D.pdf

Jim-
Thank you very much. To check my understanding, the SPI used to configure registers of the ADS5400 for operation such as 3 wire vs. 4 wire, single bus/dual bus, etc. Once I have the ADS5400 registers configured for my operation, I can apply an analog signal (in accordance to the data sheet) and the digital outputs will be available with latency as specified in the data sheet. Might there anything else that I should consider to interface with the ADS5400EVM correctly. Also, when I was checking over the header connections to ensure that they were mapped correctly, I noticed that two of the pins on the FMC-ADC-ADAPTER (Xilinx) did not match up with the corresponding pins on the ADS5400EVM header. On the ADS5400EVM header pins 64/66 are labeled DA5P/N but on the adapter board pins 64/66 are labeled FCLKN/P. I looked up the FMC LPC header information in the KC705 evaluation board user guide and the corresponding pins on the FMC header (G6/G7) have an IOSTANDARD LVCMOS18 vs LVDS. Is this a problem? Thank you for all of your information.

Adam

Hi,

Once you configure the SPI registers of the ADS5400, all you need to supply to the EVM is the sample clock and the analog input signal, and then the ADC will output the digital sample data with an LVDS DDR clock that is routed to the Samtec connector used on the EVM.    The EVM is set up such that you do not have to do any register writes by way of SPI at all just to get sample data, if you are willing to accept the default settings of all the SPI registers.    There are a few jumpers on the EVM that let you choose between 1-bus or 2-bus operation, or power down the ADC.   But still, you would get sample data leaving the EVM without having to do any SPI writes at all.    If you wanted to *change* any of the values of the configuration registers in the ADC, *then* you would have to be able to do the SPI writes.  For example, if you wanted to change the LVDS termination or drive current or adjust the gain setting or adjust offset value - then you would have to be able to SPI writes.  but you can just plug in the EVM, apply power and sample clock and analog input and the EVM will output sample data.

The pin assignment of the LVDS data pairs to that 2-segment Samtec connector on the EVM has a lot of similarity to many other of our ADC EVMs, if you were to compare, such as the DDR LVDS clock for the sample bus is always on that one corner of one of the connector segments.     But all our other many EVMs will have any number of LVDS pairs from as few as 6 to as many as 26.    But all of these other data pairs will ultimately end up at LVDS-capable input pins of the FPGA if you use the EVM with the TSW1400 capture card or the older TSW1200 capture card.    Some years back when we created the FMC-ADC-Adapter to connect to the Xilinx development platforms, we did not choose the pin assignment into the development platform.  Someone from Xilinx did, and we just built the adapter and stocked it.  But all of those other data pairs are supposed to go to LVDS-capable input pairs on the FPGA, even the pair labeled as FCLK on pins G6/G7.     If there have been any newer Xilinx development platforms since then that this is not the case any more, I am not aware of any such changes.

Now, about that data pair labeled as FCLK: that is also just another LVDS data pair, and the ADS5400 just uses it as one of the bits of the sample bus.   We also have some other EVMs in TI where the ADC uses a serialized format on the data pairs such as the AD5282 for example.  On these EVMs, there is still a DDR LVDS clock for the sample bus, but the sample data for each channel are pushed onto a single LVDS pair one bit at a time, serialized.  And then there is another LVDS pair called FCLK for frame clock that is used to identify where the msb and lsb are in the serialized data stream.  In other words, FCLK is just another data 'channel' where the data on that channel is a fixed and known pattern such that the FPGA can look to the FCLK pattern and see where the serialization boundary is on the other channels.   So it is a bit of a misnomer to call that extra channel a 'clock', but that is the name of the signal.    It is really just another data pair.  and as such, EVMs that do not have a frame clock such as the ADS5400 are free to use that LVDS pair as a data pair.

The reason I went into that description of FCLK at all is 1) because you see that name on the schematics of the adapter board and it might be confusing and 2) when the first rev A adapter board was made the name of the signal also confused the person who made the pin assignments into the FPGA and they put this signal onto an FPGA pair that was clock-capable but was not capable of being used as a general purpose LVDS IO.    The revC adapter board that is available now has this LVDS pair reassigned as per the schematics that are available on the TI website and it is now going to a regular LVDS data input - as far as I know.

Regards,

Richard P.

Richard-

This information is very helpful. Does communication via SPI need to be done through the miroblaze or can HDL be used to apply sclk, shift data onto the SDIO and toggle SEN? Thank you for your time.

Adam

Does the ADS5400EVM have data mapped to these FCLK then as it does not use it?

Nevermind about the above question. I just haven't had enough coffee. I looked at the pin out on the ADS5400EVM for the samtec and noticed that it is DA5P/DA5N.

Hi,

as for driving the SPI lines from an FPGA, the ADC does not care how the logic is implemented.   if you want to use a microcontroller in the FPGA so that you could just give the microcontroller a list of address/data pairs and let it step through them, that would be fine.  Then you could easily change the values written if needed later on.  Or if you want to just implement a state machine to set the spi enable and spi data while toggling the spi clock, that would be fine too.    For the usb device that is on the EVM to drive the SPI we just form the address data pairs into a list of bit vectors that we give the usb chip in a bit-bang fashion where we set the SEN and DSATA and SCLK on a cycle by cycle basis, first with clock low and then with clock high, etc.

Regards,

Richard P.

Hello Richard, thank you for your reply. I have another question regarding the termination resistor. I read that the receiver needs a parallel 100 ohm resistor for each LVDS data pair. The FPGA can be constrained to achieve this. I noticed that the ADS5400 has internal termination resistors (100/200) that can be configured on register 0x06. By default the register is set to no termination. Do I need to configure this register for 100 ohm termination along with a termination resistor on the receiver (FPGA) or is this an either or? Thank you for our time.

Adam

Hi,

Normally an LVDS signal is terminated at the end of the controlled impedance transmission line trace with the 100 ohm resistor, and the most convenient place for this is the integrated 100 ohm resistor available in the FPGA.    The termination is at the end of the line to avoid signal integrity issues due to stubs of unterminated trace.

The optional source termination is there to allow for a doubly terminated line in the case of poor layout or poorly matched termination at the end of the trace.   If there are signal reflections coming back from the end of the line or some discontinuity along the line, then a source termination would allow those reflections to terminate cleanly at the source instead of reflecting back and forth up and down the line until they die out.    source termination is by default off, and would normally only be used to clean up an issue later on if needed. 

Regards,

Richard P.