• State
  • Locked Locked
  • Replies 7 replies
  • Subscribers 47 subscribers
  • Views 1879 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADC32RF45 EVM exhibits a notch in the spectrum at Fs/8 intervals

Robert Bell
Prodigy 30 points
Other Parts Discussed in Thread: ADC32RF45

Product is ADC32RF45 EVM with supporting software.
Was successful in setting up and running the initial configuration suggested for board checkout. When pursuing a change of sample rate and configuring for full rate LMF8224 mode, I get a reasonable spectrum and signal. However, at multiples of Fs/8 the signal is notched. For us this is Fs=2 GHz and the notches are 250, 500 and 750 MHz. DDC's etc are disabled.]

Steps to recreate problem: Configure the EVM for a 2 Gsample clock, using synthesizer, filtering and splitter as recommended in your TI up instructions. Use LMF 8224 mode, 14 bit full rate transfer (I used the two supporting cfg files provided with the download: LMK_ADC32RF45_LMF_8224_ExtClock.cfg and ADC32RF4X_14bit_LMFS_8224.cfg). Set the capture software device selection to ADC32RF45_LMF_8224. ADC Signal input is from 250 MHz to 750 MHz @ approximately -1 dBFS in. Signal power reported is close to the -1 dBFS mark EXCEPT for 250, 500 and 750 MHz, which are variable between -60 and -50 dBFS. The notch effect disappears by +/- 100 kHz on either side of these frequencies. This suggests a digital effect to me.  Anyone have any ideas on what is causing this or can suggest some things to look for?

  • 0
    TI__Mastermind 29220 points

    Hi,

    There is actually a digital filter designed into the data path of this device that is actively filtering out those frequencies.  Since the front end of the ADC is 4-way interleaved, there is a fundamental issue with Fs/4.   If you consider that each of the four interleaved sub-ADCs is being clocked at Fs/4 (which would be 500Msps with your clock rate at 2Gsps as you describe) then for each sub-ADC an input tone right *at* Fs/4 would alias right back onto DC for that particular sub adc.  So any DC offset within the sub ADCs gets mingled with any Fs/4 tone that is coming in.  So the designers filtered out Fs/4.    You can disable the Fs/4 filter, but then there would be a spur at Fs/4 due to any interleaving mismatches remaining amongst the sub-ADCs even after the interleaving correction logic.   I do not know the SPI register bits needed to turn off the Fs/4 filtering right at the moment, but I believe these bits will be identified in the next revision of the datasheet due out very soon, or we can get this information from the design team for you.     And apparently this filtering is not just Fs/4, but also Fs/8 and at multiples of that.

    Regards,

    Richard P.

  • 0 in reply to Richard Prentice
    Prodigy 30 points

    Thanks Richard for responding. There is a register setting for the Fs/4 filter in either the ADC setup program or in the GUI somewhere but it doesn't seem to be active. Could be I am not familiar enough with the tool to be playing with bits at that low enough level yet.  We are very interested in seeing what the part can do without the filter.  The spur may be tolerable in our application.  As it stands now, there would be a hole right in the middle of our pass-band and that could introduce a post processing glitch  that is unacceptable.  Is there any chance you could have someone send out instructions on disabling the filter so we can evaluate this?

    Thanks again for your assistance,

    Bob Bell

  • 0 in reply to Robert Bell
    TI__Mastermind 29220 points

    Hi,

    I have asked our design team for the specifics on disabling this filter and will provide it when I have the information.  The datasheet on the web at present is still dated July 2016 and does not list this information I believe.  There is a new draft of the datasheet due to be released to the web soon I am told.

    Regards,

    Richard P.

  • 0 in reply to Richard Prentice
    Prodigy 30 points

    Hi Richard,

    I haven't seen anything yet from you or your team on disabling the filter.  We are fast approaching a decision point on device selection and I would like to complete an assessment of your device within the next week or so if possible. Is there anyway you can get me a quick turn around on how to disable the filter?

    Thanks,

    Bob B

  • 0 in reply to Robert Bell
    TI__Mastermind 29220 points

    Interleave_disable.cfgHi,

    what I am finding is that disabling the notch filter means disabling the interleaving correction entirely.   Please see attached for a short configuration file that can be loaded into our EVM using the SPI GUI after all other config files are loaded.   Or if not using our GUI and EVM, the config file can be read for the sequence of address/data pairs needed to accomplish disabling the interleaving correction.  Actually, this 'freezes' the interleaving correction, with the expectation that the ADC would be seeing idle channel input before freezing the correction values, and then the interleaving correction is frozen and then the input signal applied. 

    Regards,

    Richard P.

  • 0 in reply to Richard Prentice
    Prodigy 175 points

    Hi,

    Would you be able to tell me what digital correction the ADC is performing? Is it only offset correction? Or is there also gain/timing/BW digital correction?

    Thanks!

    Rosanah

  • 0 in reply to Rosanah Murugesu
    TI__Mastermind 29220 points

    Hi,

    I do not have full details of the internal logic of the device, but the correction is not for trimming gain or bandwidth.  It is primarily removing the DC offset from each of the four sub_ADCs as shown in the figure 235 of the datasheet.  Rather than repeat what I had typed in response to your other posting, may I just point to the posting here please?

    https://e2e.ti.com/support/data_converters/high_speed_data_converters/f/68/t/590119

    Regards,

    Richard P.