DAC37J82 Min Clock Rate

Moham

Hi,

My Application required clock for analog signal generation is 500 MHz and best fitted interface for it is JESD204 but when i search within TI DAC products min value of maximum update rate of these DACs reported as 1600 MHz. DAC37J82 is a case that i found for these requirements and i have questions about minimum supported update rate and possibility of NCO bypassing in this IC. Can I Use 2 Lane per converter for driving DACs direct sampling?

Thanks

over 7 years ago

0 jim s over 7 years ago

TI__Guru* 91947 points

Moham,

We are looking into this for you.

Regards,

Jim

0 jim s over 7 years ago

TI__Guru* 91947 points

Moham,

According to Table 10 of the data sheet, you can use 4211 mode, which would be 2 lanes per DAC, and the Fdac rate and Fdata rate can be anywhere from 100-1230 MSPS with Int 1X and NCO bypassed.

Regards,

Jim

0 Moham over 7 years ago in reply to jim s

Intellectual 635 points

Jim,

Thanks for your perfect and complete answer. As final question for clearance: according your answer input clock can be as low as 100 MHz without using internal PLL?

Regards

0 jim s over 7 years ago in reply to Moham

TI__Guru* 91947 points

Correct.

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DAC37J82 Min Clock Rate