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DAC3484 DATALCK and Data rate relation

Expert 1545 points
Other Parts Discussed in Thread: DAC3484, DAC3482, DAC3484EVM

Hello 

I want to use the DAC3484 with the following configuration:

DAC_REF=960MHz

Data rate for DAC1,2=240MSPS

NCO1 = OFF

Data rate for DAC3,4=100MSPS

NCO2 FREQ= 260MHz

DAC1,2 Output: Complex IQ BW of 200MHz

DAC3,4 Output: Complex IQ BW of 340-380MHz (upconvert using NCO)

My question is:

1. Is this setup applicable?

2. What is the minimum DATACLK freq? 

3. Is there a way to reduce the level of the Nyquist at the DAC1,2 output (960M - DAC_output_Freq) besides placing a low pass filter?

4. Does the FPGA MAX10 family from Altera able to drive the DAC in this setup? 

Thanks

  • Izik,

    the DAC3484 4 channel data rate must be coherent. It does not support different data rate among four channels. You will need to consider having 2 channel DAC such as the DAC3482 to support independent data rates.
  • Hi

    Yes you are right, I will drive all DACS all channels with data rate of 240MSPS.
    Please review my question again based on this information.

    Thanks
  • Izik,

    If your data rate is 240Msps, then you can use the DAC3484 to do what you want.

    DAC1,2: 240Msps, 4x interp, output rate of 960Msps, NCO not used

    -You can get approximated 200MHz of complex BW centered at 0

    DAC3,4: 240Msps, 4x interp, output rate 960Msps, NCO used

    -You can get approximated 200MHz of complex BW centered at 0, the NCO can then be used to move the complex signal between the complex BW of +/-480MHz.

    Ken.

  • Thanks
    What would be the DATACLK signal frequency in this setup?
  • Izik,

    If you look at figure 52 and figure 53 of the data sheet, you can see that the DataCLK is double datarate, it clocks in the data on the data bus at every edge. 4x 16b samples must be clocked in during each of the of the sample periods, so the frequency of the DataCLK in this case is 240Msps*2=480MHz.

    Ken
  • Thanks!

    I looked on the DAC EVB along with the TSW1400, and I have seen that there's a test point to measure DATACLK (SJP11). So I did measure it, and I noticed that its frequency changes only when the DACLCK changes, not when the data rate change. Can you please explain?

    I am using the pattern generator application by TI to generate the waveforms, and I tried 240MSPS and 300MSPS, and also one of the examples which is 307.2MSPS, and I have seen that the DATACLK changes only when DACCLK is changing.

    Can you please advise?

    SJP11

  • While I am waiting for answer to my previous question, I ask one more question on this DAC3484:

    What is the phase of the image singnal comparing to the fundamental? Suppose my output is 100MHz, my REF is 960MHz, so the image is on 800MHz. So what would be the phase of 100MHz comparing to the phase of 800MHz signal?

    Thanks
  • The datarate is just a number used for calculation and FFT purposes.  In sampled systems the datarate has no relevance to real time.  In other words it is just a reference point for the signal that is sampled - you could just call the datarate Fs for example.  Then everything is relative to this Fs when doing any kind of signal generation.  You could generate a 10MHz tone sampled at 100MHz.  Or you could say this is also a 0.1Fs signal.  If you change Fs then the signal changes frequencies - it does not have an absolute frequency unless you refer it to the sample rate.

    Since Dataclk is always related to the DACclk by the interpolation, then Dataclk will not change unless you change DAC clk or the interpolation.

  • Thank you for your answer.  However it's still not clear to me.  The DATACLK is generated by the FPGA (is this correct?).   And the  FPGA doesn't know what is the DAC reference frequency. So how does the two signals connected?

  • Have a look at figure 1 of the DAC3484EVM users guide:
    www.ti.com/.../slau432a.pdf

    This shows the clocking scheme. The clock chip sends the DAC clock to the DAC and a reference clock to the FPGA. The FPGA will in tern send back the data and a data clock to the DAC.
  • Suppose I am using the DAC just to output the NCO freq. That means that the DATA input is constant (DC), and I see at the output a CW at the NCO freq. What would be the DATACLK frequency then? (DAC Ref is still 960MHz)

    Thanks
  • In general the DAC CLK is always related to Input Datarate (sample rate if you prefer) by the interpolation factor.

    The Data CLK is always 2 clocks per sample rate clock. For a real example.
    DAC CLK=960MHz
    Interp N=4
    Datarate (or sample rate) = 960/4=240Msps
    DATACLK = 2x Datarate (IQ interleaved DDR) = 2x240=480MHz

    Regardless of the type of signal, for a robust system you need to meet the clock relationships. The only thing you can get away with for a DC signal is the setup and hold times between the DATA CLK and data are a don't care as it is constant value and there is no chance that you will clock in the wrong data.

    Ken

  • So just to make sure I understand correctly, if I want to use only the NCO, all I need is to send constant DC signal to DATA and DAC CLK/2 to the DATACLK pins? Will I still have an IQ output to drive IQ modulator?

    Thanks
  • Izik,

    Yes.

    The NCO is complex by nature - it will generate sin and cosine and multiply this into the input in a complex mixer implementation.  If the input is DC, 0Hz, then the output will be sine and cosine at the NCO frequency.

    Ken.

  • Thanks a lot