Hello Team,
We received the below question from one of our customers on synchronization of two ADS42JB69 devices:
We've developed a PCB with two ADS42JB69 ADCs connected to an FPGA with a JESD204B Subclass 2 interface. We are able to set the ADC's configuration registers via SPI to generate different test patterns, but they start with different phases, even applying a SYNC signal.
How can we use the test patterns to verify the synchronization between the two ADCs?
Thank you in advance!
Kind regards,
Mo.