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ADS42JB69 synchronization

Other Parts Discussed in Thread: ADS42JB69

Hello Team,

We received the below question from one of our customers on synchronization of two ADS42JB69 devices:

We've developed a PCB with two ADS42JB69 ADCs connected to an FPGA with a JESD204B Subclass 2 interface. We are able to set the ADC's configuration registers via SPI to generate different test patterns, but they start with different phases, even applying a SYNC signal.

How can we use the test patterns to verify the synchronization between the two ADCs?

Thank you in advance!

Kind regards,

Mo.

  • Mo.,

    I am checking with the design team regarding this. I am not sure, but the test patterns may not reset with respect to SYNC.  Can they try this test with a common sinewave sent to both ADC's? Are both ADC's receiving synchronized sample clock? Is SYNC edge being sampled at the same time by both parts? Is the FPGA using two separate cores to capture the data? Is there a chance the FPGA is the problem? The SYNC signal needs to arrive and be sampled by all parts in this link at the same time. Any reason why they did not want to use subclass 1?

    Regards,

    Jim 

  • Mo.,

    Test patterns (Ramp) are free running and can’t be reset or synchronized.

    Regards,

    Jim

  • Hi Jim,

    Thanks a lot for the clarification.

    Kind regards,
    Mo.