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ADS54j60

Other Parts Discussed in Thread: ADS54J60, ADS54J20, DAC37J84, LMK04828, ADS54J42

Hello,

I am trying to use your ADS54J60 EVM.  I want to use the internal SYNC to make the ADC transmit coninious K28.5 CGS on its 4 JESD output lanes.

I added these changes to ADS54J20_LMF_4211.cfg:

0x690001 0xC4 
0x690002 0x40 

Is this all I need to do?   Seems like this did not work

I tried to use the low level page of the ADS54Jxx GUI V1.6 to check this, seems like that page does not work correctly.

Please help, I really need to get this working.

Thanks,

John Reyland

Rockwell Collins, Inc

  • John,

    When I write to these addresses, then do a read, I get the correct value back (see below). Do you not get this with your GUI? I am double checking with the design team that these two register writes will do what you want. Can you tell me what FPGA you are trying to interface too? If you can tell the FPGA vendor and the ADC sample rate and LMFS settings, I can help you with getting your link up.

    Regards,

    Jim

  • Hi Jim,

    I am plugging your ADS54J60 Eval card into FMC2 connector of the VC707 Virtex 7 eval card. I have a DAC 37J84 Eval card plugged into FMC1; that JESD works great, really like that DAC.

    So the DAC FMC1 JESD is a transmit only and the ADC FMC2 JESD is a receive only. The Xilinx Vivado IP is setup in verilog, our local Xilinx FAE has checked it several times for any obvious problems.

    I checked that the Sync command wire, 6.144 MHz SysRef clock and 122.88 MHz FGPA clock are all coming through the FMC2. ( Hint: to make the FPGA clock drive the FMC2 you have to short out C79 amd C80. This is because the FPGA card also has a pair of coupling caps.)

    I'm trying to setup the ADC to spew out K28.5 code group sync continuously. Tough part is, there is no easy way to verify the serial data on the lines between the ADC JESD outputs and the FPGA GTX (serial JESD transciever) inputs. So if the receive JESD indicates no CGS, how can you tell if it's the ADC or the JESD?

    Right after the FPGA starts, the FMC2 JESD sets SYNC = 0 (active sync command to the ADC). Then SYNC never goes high again! The ADC seems to be transmitting random data.

    Below are all my system parameters. I have been working on this for two weeks, please help!

    Thanks,
    John Reyland

    JESD Parameters for ADC ADS54J60 to FMC2 to Virtex 7, LMFS = 4211

    L = 4 = number of lanes
    M = 2 = number of ADCs transmitting over JESD link
    F = 1 = number of octets/(frame and per lane)
    S = 1 = number of samples/frame (i.e. each ADC sends 1 samples in each frame)
    K = 20 = frames/multiframe

    ADC sample clock = 491.52 MHz
    Each ADC output occupies 2 lanes
    Frame clock = core_clock = frequency set to deliver 32 bits/lane on JESD output
    Frame clock = 491.52/4 = 122.88 MHz
    JESD line rate = 40*(frame clock) = 4915.4 MHz
    SysRef frequency = (Line rate)/(10*K*4) = 4915.4/(10*20*4) = 6.144 MHz
    LMFC rate = 24.5770 MHz
  • John,

    See if these two documents help you.

    Regards,

    Jim

    LMF_8224_Fs_983p04M.pptxSLAU580B.pdf

  • Hi Jim,

    I read the documents you sent, thanks. I am not sure the interposer card will work. It is setup for FMC1 and I am trying to use FMC2 on the VC707 card. The High Speed Data Converter Pro TSW14J10_ZC706.bit constraints file is probably complied to use FMC1. I really need FMC2 because I have the DAC37J84 EVM plugged into FMC1 (they fit side by side)

    Seems like the problem is either that the ADS54J60 eval card is not being setup properly (I studied the setup files TI provides as well as the data sheet thoroughly, also you seem convinced that the setup works). Or there is something wrong with my Virtex 7 JESD Verilog code.

    I was dismayed that I tried to put the ADC into continuous CGS mode (0x690001 = 0xC4 and 0x690002 = 0x40 ) and nothing changed. When I trigger on ADC JEsD reset, I see SYNC to the ADC always low and just random bits coming out of the JESD Phy. So either the GTX transceivers are not functioning or the ADC is not outputting correctly.

    I'm going to order the interposer card however in the mean time a useful test may be to setup the ADC JESD on FMC1 and see it works.

    Thanks,
    John Reyland
  • John,

    For a sanity check, did you try just the ADC on FMC1? Are you using both a Reference clock and Core clock with your firmware? This is required with the firmware Xilinx developed for us. This was the main reason I sent the documents, to point this out. 

    Regards,

    Jim

  • John,

    LINK layer mode is to send patterns for test. To send K28.5, only write to 0x690001 with 0xC4 and do not send write to address 0x690002.

    Regards,

    Jim

  • Hi Jim,

    Yes I am running the ADS54J60 eval card on the Virtex 7 FMC1 connector.

    You sent me the following comment, "To send K28.5, only write to 0x690001 with 0xC4 and do not send write to address 0x690002." However in the file "ADS54J60_test_K28p5.cgf" , written by someone from TI, I see:

    ADS54Jxx_DIGITAL
    0x6800f7 0x01 // digital reset
    0x680000 0x01 //reset digital
    0x680000 0x00 //clear reset
    0x690007 0x09 //set internal defaults JESDV and subclass V
    0x690000 0x80 //set CTRL K
    0x690002 0x40 // K28.5 pattern
    0x690006 0x0F //set K to 16


    This is pretty much the opposite of your advice. Is this another valid way to send K28.5? Or is the file "ADS54J60_test_K28p5.cgf" just incorrectly written?

    Thanks,
    John Reyland
  • John,

    There are two ways to get K28.5:

    Using SPI sync – 0x690001. This forces the SYNC input low and causes the part to output K28.5 characters.

    Using link layer mode – 0x690002. The link layer will send K28.5 independent of the status of the SYNC input.

     

    If the link layer is set, it overrides the SPI sync.

    Regards,

    Jim

  • Hi Jim,

    Thanks for the info on how to send K28.5 over my ADS54J60 Eval to FMC1 to VC707 Virtex eval card.  

    I start this up by downloading LMK04828 config file, pressing the reset on the ADS54J60 and then downloading the ADS54J60 config file.  I make sure PLL1 lock LED is on.  Then I run Xilinx Vivado Integrated Logic Analyzer (ILA, used to be called ChipScope) to look at the JESD Sync, 8 lane data, and 256 bit final output.  I get one of three results:

    1. Sync output to ADS54J60 is always low and ADC does not seem to respond

    2. Sync output to ADS54J60 seems to cycle up and down, no useful data come out.

    3. Sync output goes high, and data comes out normal.  I can extract sample stream and take spectrum to check.

    In other words, I can't get this link to be reliable.  I'm using TI written setup config files (changing JESD mode to 20X).

    My Xilinx FAE friend has checked my Verilog code.  I have ordered your ADS54J42 EVM to see if that works better.  Why is your DAC37J84 EVM so easy to use (same Verilog code setup) and the ADS54J60 so seemingly impossible?

    One more thing, you asked me why I am using 8 lanes.  Good question.  Four lanes on FMC2 causes complicated clocking errors.  Here is a description quoted from our local Xilinx FAE:

    "With the 8 lanes, it was probably completely using 4 channels in each quad, and the IP core was creating 2 GT_COMMON blocks, one for each quad [this works well].  With 4 channels, it would be just as easy, except that these 4 channels are not in a single quad, but placed across two quads [this causes problems].  This means that a second GT_COMMON block is required, but the IP doesn’t know that they are placed across 2 quads, so it only includes a single GT_COMMON."

    Best Regards,

    John Reyland

     

  • John,

    Does your version of firmware use both a reference clock and core clock like the firmware Xilinx designed for us? If not, I am wondering if this may be the cause of some of your problems. The ADS54J42 uses the same core as the ADS54J60, and will give you the same results. This is not issue with our TSW14J56EVM, which is Altera based, so I find it hard to believe it is an issue with the ADC. If you can send us your firmware, I can ask the Xilinx team we deal with to take a look at it. This group actually designed the JESD IP.

    Regards,

    Jim 

  • Hi Jim,

    I appreciate your concern.  To reduce sources of confusion, I am using your "LMK_983p04_8224_VC707.cgf" and also your "ADS54J60_LMF_8224.cfg  so my setup has the following characteristics:

    LMFS = 8224

    LMK04828 VCO1 = 24*122.88 = 2949.12 MHz

    Fs =  VCO1 /3 =  983.040 MHz

    FPGA Clk =  VCO1 /12 = 245.76 MHz

    Core Clk = VCO1 /24 =  122.88 MHz

    Sysref = VCO1/768 = 3.84 MHz

    Fline = 20*FPGA Clk = 4.9152 GHz

    K = frames/multiframe = 32

    I noticed something strange.   Sometimes when I load "LMK_983p04_8224_VC707.cgf"  the PLL2 lock LED come on and the LMK04828 FPGA Clk output starts and quickly goes away (I have a high impedance scope probe connected to a little wire soldered to C80 on the ADC card).  This happens even if the ADC card is not connected to FMC1.   After a few loads, the FPGA clock stays on.     I am not imagining this, if you were here I could show you.  

    My Verilog JESD setup code is so simple, I will copy it below.  You can see that it mostly matches Xilinx JESD204 document, PG066, Figure 3-1.   Only thing missing is the constraints file and a program that provides the AXI interface.    I can send you the whole project if you tell me how.

    Thanks for sticking with me,

    John Reyland

    Here is the main code that hooks up the clocks and the JESD:

    //---------------------------------------------------------------------
    // Title : Hardware Demo design top level for JESD204 on VC707

    module jesd204_zc706 (

    // 200 MHz system clock from VC707
    input clk200_p,
    input clk200_n,

    // External Reset pushbuttons on the VC707
    input DSPreset_sw, // CENTER
    input ADC_resync_sw, // NORTH

    // Status LEDs
    output[7:0] leds,

    input [7:0] rADCxp,  JESD PHY parallel line outputs
    input [7:0] rADCxn,

    // JESD _SYNC command to ADC
    output SyncADC_p,
    output SyncADC_n,

    // GTX ref clock in from the adc card
    input ADCrefclk_p,
    input ADCrefclk_n,

    // SysRef clock from LMK04828
    input SysRefADC_p,
    input SysRefADC_n,

    // JESD CoreClk from LMK04828
    input LAO_p,
    input LAO_n,
    );


    // _SYNC output to ADC card
    OBUFDS adcsync_obuf (
      .O (SyncADC_p),
      .OB (SyncADC_n),
      .I (adc_core_resync)
    );

    // These clocks are from LMK04828 on ADS54J60 Demo card
    // These are all divided down from VCO1 = 2949.12 MHz

    // SysRef Clock from ADC card
    // LMK04828 generates this as VCO1/768 = 3.82 MHz
    IBUFDS adcsysRef_ibuf (
    .I (SysRefADC_p),
    .IB (SysRefADC_n),
    .O (sysrefadc)
    );

    // JESd PHY Ref Clock from ADC card
    // LMK04828 generates this as VCO1/12 = 245.76 MHz
    IBUFDS_GTE2 ADCrefclk_ibuf (
    .I (ADCrefclk_p),
    .IB (ADCrefclk_n),
    .O (ADCrefclk)
    );

    // Core Clock from ADC card
    // LMK04828 generates this as VCO1/24 = 122.88 MHz
    IBUFDS LAO_ibuf (
    .I (LAO_p),
    .IB (LAO_n),
    .O (ADCcoreclk)
    );

    // 200 MHz system clock from ZC706

    IBUFDS clk200_ibuf (
    .I (clk200_p),
    .IB (clk200_n),
    .O (clk200)
    );

    BUFG clk200_bufg (
    .I (clk200),
    .O (clk200b)
    );

    // MMCM generates local clocks from 200 MHz input
    // CLKOUT0 : clk100 100 MHz - AXI Lite interface
    // CLKOUT1 : clk10 10 MHz - slow clock for long resets etc

    //Clocks below come from an MMCM, not shown to save space.

    BUFG clk100_bufg (
    .I (clk100b),
    .O (clk100)
    );

    BUFG clk10_bufg (
    .I (clk10b),
    .O (clk10)
    );


    // USe a push button to reset JESD
    always @(posedge ADCcoreclk )
    begin
    if(!ADC_resync_sw) begin
    adc_reset_sw_ctr <= 30'b0; // debounce counter
    adc_core_reset <= 1'b0;
    end
    else begin
    if (adc_reset_sw_ctr < 30'b011000000000000000000000000000 ) begin
    adc_reset_sw_ctr <= adc_reset_sw_ctr + 1;
    end
    if (adc_reset_sw_ctr == 30'b010000000000000000000000000000 ) begin
    adc_core_reset <= 1'b1;
    end
    if (adc_reset_sw_ctr == 30'b010000000000000000000000000010 ) begin
    adc_core_reset <= 1'b0;
    end
    end
    end
    //////////////////////////////////////////////////////////////////////////////////////////////////

    // DSPreset actually is used only to start the AXI configuration write to the JESD
    always @(posedge clk100 )
    begin
    if(!DSPreset_sw) begin
    DSPreset_sw_ctr <= 30'b0; // debounce counter
    DSPreset <= 1'b0;
    end
    else begin
    if (DSPreset_sw_ctr < 30'b011000000000000000000000000000 ) begin
    DSPreset_sw_ctr <= DSPreset_sw_ctr + 1;
    end
    if (DSPreset_sw_ctr == 30'b010000000000000000000000000000 ) begin
    DSPreset <= 1'b1;
    end
    if (DSPreset_sw_ctr == 30'b010000000000000000000000000011 ) begin
    DSPreset <= 1'b0;
    end
    end
    end


    //===================================
    // ADC Receive JESD204 core
    //===================================
    jesd204_0_1 adc_jesd204 (
    .rx_reset (adc_core_reset), // input tx_reset
    .rx_reset_done (radcx_reset_done), // input tadcx_reset_done

    .rx_core_clk (ADCcoreclk), // input tadcx_core_clk
    .rx_sysref (sysrefadc), // input tadcx_sysref

    .rx_reset_gt (radcx_reset_gt), // output tadcx_reset_gt

    // Rx AXI-S interface clock and reset
    .rx_aresetn (rx_aresetn), // output tadcx_aresetn

    .rx_sync (adc_core_resync), // output tadcx_sync

    //Output Data from Core
    .rx_tdata (radcx_tdata), // output [127 : 0] tadcx_tdata
    .rx_tvalid (radcx_tready), // output tadcx_tready

    // Input Data to GTs
    // Lane 0
    .gt0_rxdata (gt0_adc_rxdata),
    .gt0_rxcharisk (gt0_adc_rxcharisk),
    .gt0_rxdisperr (gt0_adc_rxdisperr),
    .gt0_rxnotintable (gt0_adc_rxnotintable),

    // Lane 1
    .gt1_rxdata (gt1_adc_rxdata),
    .gt1_rxcharisk (gt1_adc_rxcharisk),
    .gt1_rxdisperr (gt1_adc_rxdisperr),
    .gt1_rxnotintable (gt1_adc_rxnotintable),

    // Lane 2
    .gt2_rxdata (gt2_adc_rxdata),
    .gt2_rxcharisk (gt2_adc_rxcharisk),
    .gt2_rxdisperr (gt2_adc_rxdisperr),
    .gt2_rxnotintable (gt2_adc_rxnotintable),

    // Lane 3
    .gt3_rxdata (gt3_adc_rxdata),
    .gt3_rxcharisk (gt3_adc_rxcharisk),
    .gt3_rxdisperr (gt3_adc_rxdisperr),
    .gt3_rxnotintable (gt3_adc_rxnotintable),

    // Lane 4
    .gt4_rxdata (gt4_adc_rxdata),
    .gt4_rxcharisk (gt4_adc_rxcharisk),
    .gt4_rxdisperr (gt4_adc_rxdisperr),
    .gt4_rxnotintable (gt4_adc_rxnotintable),

    // Lane 5
    .gt5_rxdata (gt5_adc_rxdata),
    .gt5_rxcharisk (gt5_adc_rxcharisk),
    .gt5_rxdisperr (gt5_adc_rxdisperr),
    .gt5_rxnotintable (gt5_adc_rxnotintable),

    // Lane 6
    .gt6_rxdata (gt6_adc_rxdata),
    .gt6_rxcharisk (gt6_adc_rxcharisk),
    .gt6_rxdisperr (gt6_adc_rxdisperr),
    .gt6_rxnotintable (gt6_adc_rxnotintable),

    // Lane 7
    .gt7_rxdata (gt7_adc_rxdata),
    .gt7_rxcharisk (gt7_adc_rxcharisk),
    .gt7_rxdisperr (gt7_adc_rxdisperr),
    .gt7_rxnotintable (gt7_adc_rxnotintable),


    .rx_frame_error (), // output [31 : 0]
    .rxencommaalign_out (adccommaAlign),
    .rx_start_of_frame (radcx_sof), // output [3 : 0] tadcx_start_of_frame
    // .rx_start_of_multiframe (radcx_somf), // output [3 : 0] tadcx_start_of_multiframe

    // AXI Ports
    .s_axi_aclk (clk100), // input s_axi_aclk
    .s_axi_aresetn (radcx_axi_aresetn), // input s_axi_aresetn,

    .s_axi_awaddr (radcx_axi_awaddr), // input [31:0] s_axi_awaddr,
    .s_axi_awvalid (radcx_axi_awvalid), // input s_axi_awvalid,
    .s_axi_awready (radcx_axi_awready), // output s_axi_awready,
    .s_axi_wdata (radcx_axi_wdata), // input [31:0] s_axi_wdata,
    .s_axi_wstrb (4'b1111), // input [3:0] s_axi_wstrb,
    .s_axi_wvalid (radcx_axi_wvalid), // input s_axi_wvalid,
    .s_axi_wready (radcx_axi_wready), // output s_axi_wready,
    .s_axi_bresp (radcx_axi_bresp), // output[1:0] s_axi_bresp,
    .s_axi_bvalid (radcx_axi_bvalid), // output s_axi_bvalid,
    .s_axi_bready (radcx_axi_bready), // input s_axi_bready,
    .s_axi_araddr (radcx_axi_araddr), // input [31:0] s_axi_araddr,
    .s_axi_arvalid (radcx_axi_arvalid), // input s_axi_arvalid,
    .s_axi_arready (radcx_axi_arready), // output s_axi_arready,
    .s_axi_rdata (radcx_axi_rdata), // output[31:0] s_axi_rdata,
    .s_axi_rresp (radcx_axi_rresp), // output[1:0] s_axi_rresp,
    .s_axi_rvalid (radcx_axi_rvalid), // output s_axi_rvalid,
    .s_axi_rready (radcx_axi_rready) // input s_axi_rready,
    );
    //------------------------------------------------------------
    // Instantiate the JESD204 PHY core
    // Lowest level IP that connects to the GTX
    //------------------------------------------------------------

    jesd204_phy_0_1 i_jesd204_adc_phy (

    // Output Data from GTs
    // Lane 0
    .gt0_rxdata (gt0_adc_rxdata),
    .gt0_rxcharisk (gt0_adc_rxcharisk), // output
    .gt0_rxdisperr (gt0_adc_rxdisperr), // output
    .gt0_rxnotintable (gt0_adc_rxnotintable), // output

    .gt0_txcharisk (4'b0000), // unused input
    .gt0_txdata (32'b0000000000000000), // unused input

    // Lane 1
    .gt1_rxdata (gt1_adc_rxdata),
    .gt1_rxcharisk (gt1_adc_rxcharisk), // output
    .gt1_rxdisperr (gt1_adc_rxdisperr), // output
    .gt1_rxnotintable (gt1_adc_rxnotintable), // output

    .gt1_txcharisk (4'b0000), // unused input
    .gt1_txdata (32'b0000000000000000), // unused input

    // Lane 2
    .gt2_rxdata (gt2_adc_rxdata),
    .gt2_rxcharisk (gt2_adc_rxcharisk), // output
    .gt2_rxdisperr (gt2_adc_rxdisperr), // output
    .gt2_rxnotintable (gt2_adc_rxnotintable), // output

    .gt2_txcharisk (4'b0000), // unused input
    .gt2_txdata (32'b0000000000000000), // unused input

    // Lane 3
    .gt3_rxdata (gt3_adc_rxdata),
    .gt3_rxcharisk (gt3_adc_rxcharisk), // output
    .gt3_rxdisperr (gt3_adc_rxdisperr), // output
    .gt3_rxnotintable (gt3_adc_rxnotintable), // output

    .gt3_txcharisk (4'b0000), // unused input
    .gt3_txdata (32'b0000000000000000), // unused input

    // Lane 4
    .gt4_rxdata (gt4_adc_rxdata),
    .gt4_rxcharisk (gt4_adc_rxcharisk), // output
    .gt4_rxdisperr (gt4_adc_rxdisperr), // output
    .gt4_rxnotintable (gt4_adc_rxnotintable), // output

    .gt4_txcharisk (4'b0000), // unused input
    .gt4_txdata (32'b0000000000000000), // unused input

    // Lane 5
    .gt5_rxdata (gt5_adc_rxdata),
    .gt5_rxcharisk (gt5_adc_rxcharisk), // output
    .gt5_rxdisperr (gt5_adc_rxdisperr), // output
    .gt5_rxnotintable (gt5_adc_rxnotintable), // output

    .gt5_txcharisk (4'b0000), // unused input
    .gt5_txdata (32'b0000000000000000), // unused input

    // Lane 6
    .gt6_rxdata (gt6_adc_rxdata),
    .gt6_rxcharisk (gt6_adc_rxcharisk), // output
    .gt6_rxdisperr (gt6_adc_rxdisperr), // output
    .gt6_rxnotintable (gt6_adc_rxnotintable), // output

    .gt6_txcharisk (4'b0000), // unused input
    .gt6_txdata (32'b0000000000000000), // unused input

    // Lane 7
    .gt7_rxdata (gt7_adc_rxdata),
    .gt7_rxcharisk (gt7_adc_rxcharisk), // output
    .gt7_rxdisperr (gt7_adc_rxdisperr), // output
    .gt7_rxnotintable (gt7_adc_rxnotintable), // output

    .gt7_txcharisk (4'b0000), // unused input
    .gt7_txdata (32'b0000000000000000), // unused input

    // Reset Inputs for each direction
    .rx_reset_gt (radcx_reset_gt),
    .tx_reset_gt (1'b1), // CMS (rx_reset_gt),

    .rx_sys_reset (adc_core_reset),
    .tx_sys_reset (1'b1),

    // Reset Done for each direction
    .rx_reset_done (radcx_reset_done),
    .tx_reset_done (),

    // PRBS mode
    .gt_prbssel (3'b000), /// input

    // Common input ports
    .qpll_refclk (ADCrefclk),

    .common0_qpll_clk_out (),
    .common1_qpll_clk_out (),

    .rxencommaalign (adccommaAlign),

    // Clocks
    .tx_core_clk (ADCcoreclk), // input
    .txoutclk (),
    .rx_core_clk (ADCcoreclk),
    .rxoutclk (),
    .drpclk (clk100),

    // Serial ports
    .rxn_in (rADCxn),
    .rxp_in (rADCxp),
    .txn_out (),
    .txp_out ()
    );

    //===================================
    // JESD AXI Interface Controller

    // SEts up internal JESD params, see  Xilinx PG066

    // I am not really sure this is needed
    //===================================
    axi_adc_controller i_axi_adc_controller(
    .clk (clk100),
    .rst (DSPreset),

    // Control Interface
    .rd_req (1'b0),
    .wr_req (1'b0),
    .cfg (2'b0),
    .cfg_req (1'b0),
    .address (12'b0),
    .wr_data (32'b0),
    .rd_data (32'b0),

    // AXI-Lite bus interface
    .axi_aresetn (radcx_axi_aresetn), // JESD input
    .axi_awaddr (radcx_axi_awaddr), // JESD input
    .axi_awvalid (radcx_axi_awvalid), // out -> in
    .axi_awready (radcx_axi_awready), // in <- out
    .axi_wdata (radcx_axi_wdata), // JESD input
    .axi_wvalid (radcx_axi_wvalid), // out -> in
    .axi_wready (radcx_axi_wready), // in <- out
    .axi_bresp (radcx_axi_bresp), // in <- out
    .axi_bvalid (radcx_axi_bvalid), // in <- out
    .axi_bready (radcx_axi_bready), // out -> in
    .axi_araddr (radcx_axi_araddr), // JESD input
    .axi_arvalid (radcx_axi_arvalid), // out -> in
    .axi_arready (radcx_axi_arready), // in <= out
    .axi_rdata (radcx_axi_rdata), // in <- out
    .axi_rresp (radcx_axi_rresp), // in <- out
    .axi_rvalid (radcx_axi_rvalid), // in <- out
    .axi_rready (radcx_axi_rready), // out -> in

    .busy_vio (),
    .busy_cfg (),
    .init_start (),
    .cfg_out (),
    .status ()
    );

    endmodule

  • John,

    When I duplicated your test, I never saw the FPGA clock go away. When this occurred, did you look at the status of this output clock on the ADC GUI? The divider should be 12, the DCLK source should be "Divider", and the DCLK Type should be "LVDS".

    Why does your code call out the first module as "jesd204_zc706" when you are targeting a VC707?  Why are you using a K of 32? The config file uses 16. What is the current limit set to on the ADC external power supply?

    Instead of monitoring C80, can you divide down this clock on the FPGA board and assign it to an LED? This is what the Xilinx provided firmware does, along with the core clock and system clock. It comes in handy quite often.

    Regards,

    Jim 

  • Hi Jim:

    First here are answers to you previous questions

    "When I duplicated your test, I never saw the FPGA clock go away. When this occurred, did you look at the status of this output clock on the ADC GUI? The divider should be 12, the DCLK source should be "Divider", and the DCLK Type should be "LVDS"."

    At one point, I run the ADS eval card unconnected to the FMC1 connector.  This means the LMK clock outputs were not terminated,  Maybe that damage them.

    "Why does your code call out the first module as "jesd204_zc706" when you are targeting a VC707?  Why are you using a K of 32? The config file uses 16. What is the current limit set to on the ADC external power supply?"  

    This code was originally written for a ZC706 card.   I changed K to 16.  Current limit is about 1AMP. 

    "Instead of monitoring C80, can you divide down this clock on the FPGA board and assign it to an LED? This is what the Xilinx provided firmware does, along with the core clock and system clock. It comes in handy quite often."

    I have the blinking LED on the VC707.   I also have the Xilinx diff clock pins set to LVDS.  Except for the GTX ref clk (JESD clk), these pins are fixed by Xilinx

    More questions please

     I noticed that when I reset the Xilinx program the ADS eval card current zoomed up. 

    To prevent any DC paths going across FMC1, I swapped ADS eval card R38, R39 (JESD_SYSREF) with C79, C80 (JESD_CLK).   Seems like JESD_SYSREF should be AC coupled and also FPGA_JESD_CLk already has a coupling cap on the VC707.    What do you think of that change please?    

    Now I can't get PLL2 LED to light up at all.  These three boards (two ADS54J60 and one ADS54J42) all came from Mouser Electronics.  Do you think you could send me an ADS54J60 card that you know works?

    Thanks,

    John Reyland

  • John,

    Please set the current limit to 3A. I do not think 1A is enough. Do not change the parts as we are advising customers to DC couple SYSREF to avoid any false triggering when SYSREF is disabled.  Try checking everything one more time with the current limit increased. If this does not fix it, I can probably send you a new board but would like to get the others back so we can test them. Please send me your phone number and address that we can ship this to.

    Regards,

    Jim