This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Multiple DAC3171 Synchronization

Other Parts Discussed in Thread: DAC3171

Can someone provide a detailed explanation for synchronizing multiple DAC3171 devices for a phase coherent output.  Here's what's stated in the datasheet with no further explanation on how this works:

7.4.1 Synchronization Modes

There are three modes of syncing included in the DAC31x1: NORMAL Dual Sync, SYNC ONLY, and SIF_SYNC.

• NORMAL Dual Sync: The SYNC pin is used to align the input side of the FIFO (write pointers) with the A(0)

sample. The ALIGN pin is used to reset the output side of the FIFO (read pointers) to the offset value.

Multiple chip alignment can be accomplished with this kind of syncing.

  • Hi,

    please take a look at the following application note, particularly section 2.4.

    This application note covers the DAC328x family as well as the DAC3171 and similar devices.   The purpose of the FIFO on the digital channel is to decouple the data clock for the digital bus from the sample clock for the DAC output.   The usual clocking architecture would be a clean low-jitter clock source for the DACCLK of the DAC, with a copy of this clock provided to the FPGA.   The FPGA would then take this copy of the clock and generate the sample data out of the FPGA along with a data clock.   Without the FIFO in the DAC, the user would have to control the timing of the data from the FPGA to match the timing needed at the input of the DAC.   With the FIFO, the user need not worry about the timing of the path from the clock source to the FPGA and then to the DAC.  The FIFO absorbs any phase mismatch.

    But with the FIFO comes a possible variation in latency through the FIFO from one device to the next or even one power cycle to the next.   To control the latency through the FIFO, there are signals to reset the FIFO pointers for the write side and the read side very precisely.   The SYNC signal resets the FIFO write side, and for multi-device synchronization you would need for every DAC to get the same DATACLK and the SYNC signal on the same edge of DATACLK for every device.  This makes every device reset the FIFO write pointers in unison.    Then at the same time the ALIGN signal is used to reset the FIFO read side.   For multi-device synchronization you would need for every DAC to get the same DACCLK and the ALIGN signal on the same edge of DACCLK for every device.   This makes every device reset the FIFO read pointers in unison.   Now the latency through all the FIFOs would be the same across all devices.    Note though that the SYNC signal must satisfy setup/hold timing around the DATACLK into the DACs, while the ALIGN signal must satisfy setup/hold timing around the DACCLK.  So the FPGA would be the likely source for the SYNC signal along with the DATACLK and data, while the ALIGN signal is likely sourced by the same device as drives the DACCLK.

    Regards,

    Richard P.

  • Thanks... this answers my question.

  • I have an additional question:

    The datasheet for DAC3171 does not appear to specify setup and hold timing for the align signal. From the app note you attached there are similar DACs that do have this specified, both are equivalent with 0 ps for setup and 300 ps for hold. Can you provide the S/H times for the DAC3171?

    Regards,

    Rick Z.
  • Hi,

    I have asked for this information from the design team as I don't see it in the datasheet either. 

    Regards,

    Richard P.

  • Hi,

    The characterization data for the setup/hold time for the ALIGN input relative to DACCLK was never collected.   The data is being taken now for inclusion in the datasheet as well as answering your question as soon as I can.   It is being worked on, but I will ask for an estimated completion date so we can know about when I will be able to provide this data for you.

    Regards,

    Richard P.