ADC3444EVM firmware description

Ramakrishna Bachimanchi

Other Parts Discussed in Thread: ADC3444EVM

Hi,

I recently purchased ADC3444EVM and TSW1400 and in the process of getting it set up to do some testing. I also downloaded the quartus files for the set up and was trying to understand the code, but I don't code in verilog. Is there a firmware description document which explains how the SERDES, PLL, DPA etc. are set up for the data acquisition? I would like to understand the code rather than just loading the files came with the evaluation software

Thanks,

Ramakrishna

over 7 years ago

0 jim s over 7 years ago

TI__Guru* 91947 points

Ramakrishna,

Attached is some info that may help you.

Regards,

Jim

7870.TSW1400_doc_adc.pdf

0 Ramakrishna Bachimanchi over 7 years ago in reply to jim s

Intellectual 300 points

HI Jim,
this document is very helpful and answers most of my questions. Only thing I am trying to get my head around is with a deserialization factor of 4 and the adc is 14 bit (7 bits on each data line), I am not sure how the acquisition works. It suggests, it acquires 4 bits every clock_adc, how does it get the whole sample. In two clocks, it will be 8 bits? Will you please explain this one. I am probably missing something here. This being an adc with odd bits per frame clock per data line(in 2 wire mode), it is very confusing.
Thanks,
Ramakrishna

0 Ken C over 7 years ago in reply to Ramakrishna Bachimanchi

TI__Genius 12965 points

Please look at the data sheet figure 134. It shows the 2 wires per ADC channel and the 7x serialization along with the FCLK and CLK. The MSB and LSB bits are split across 2 lanes with 7 bit clocks per sample clock.

Ken.

0 Ken C over 7 years ago in reply to Ken C

TI__Genius 12965 points

Dis-regard my previous post. I see it is in reference to the firmware and not the ADC outputs. We will get back to you soon.

Ken

0 Ramakrishna Bachimanchi over 7 years ago in reply to Ken C

Intellectual 300 points

Hi Ken,
that is correct. This is in reference to the Firmware. It is confusing as I am trying to understand the bit slip mechanism too. As I see FCLK will be 7 bits too, if sampling with DDR, but it also had deserialization factor of 4
Ramakrishna

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ADC3444EVM firmware description