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ADS54J60

Other Parts Discussed in Thread: LMK04828, ADS54J60

Hello Jim.

I asked you some previous questions about the ADS54J60 demo card.  Seems like I have it working now, one of my problems was current limiting the +5VDC.  Another problem was I needed to run SysRef from the LMK04828 into the Xilinx JESD IP.  Thanks for all you help. 

One more question please.  Is there ADS54J60 setup that will stop the initial lane alignment from transmitting (in subclass 1)?

Thanks,

John Reyland

  • John,

    Glad to hear you are running. If you set bit 0 to a 1 in register 0 of JESD Digital Page 6900h, this will disable the ILA sequence.

    Regards,

    Jim 

  • Hi Jim,

    If I turn off ILA on the ADC and the Xilinx JESD so that I am only relying on CGS does that mean my JESD lane reception may produce out of order samples?

    Thanks,

    John Reyland

  • Hi Jim,

    Seems like no matter what I do I can't get the ADS54J60 to send ILA pattern in subclass 1.   Also, when SYNC goes low, I get a long string of 0 lanes prior to CGS..  What do you think is going on here?  I am using the TI Ads54J60 GUI and setup files.   Thanks,  John Reyland

    On the left side, adc_core_resync goes low and then lots of 0 lanes and then lots of bcbcbcbc and then when SYNC goes high ADC starts spewing out samples, no ILA!   I tried all the settings in register 690000

  • John,

    If you write a 0x80h to register  6900, you should see the following ILS sequence as shown below. If you are not seeing this, can you send a screen shot of what you are seeing?

    Regards,

    Jim

  • ILA Sequence.pptxJohn,

    The screen shot is attached.

    Jim

  • Hi Jim,

    Thanks for the ILA info.  Here is a lot of info about my setup.    You can call me at 319 295 4458 if you have questions.   Thanks, John

    Xilinx Vivado JESD interface to ADS54J60 Startup 8 lane sync
     
    Problem: JESD interface, Xilinx VC707 card to ADS54J60 eval card.
    In Subclass 1, ADS54J60 send CGS and Xilinx raises _SYNC however then samples start coming over instead of ILA pattern
     
    Sample rate = 614.4 MHz
    Subclass 1, JESD RefClk = 153.6 MHz
    SysRef = 2.4 MHz
    K = 16
     
    ADC setup file:
     
    LMK04828
    0x10F 0x66 //Enable SYSREF to ADC
    ADS54Jxx_ANALOG
    0x0000 0x81 // LMF = 8224
    0x0011 0x80
    0x0059 0x20 // always write 1 to bit 5
    ADS54Jxx_DIGITAL
    0x6800f7 0x01 // digital reset
    0x680000 0x01 // reset digital
    0x680000 0x00 // clear reset
    0x690000 0x80 // set CTRL K
    0x690006 0x0F // set K to 16
    LMK04828
    0x10F 0x06 //Disable SYSREF to ADC
     
    Top lever showing _SYNC going low and CGS pattern
      
     
    Expansion around the end of CGS. Note Xilinx expects ILA. Adc_core_resync (_SYNC) goes high but toggles low at end of LMFC cycle (6th signal from bottom). Because of missing ILA?
      
     
    Further expansion around the end of CGS. Note Xilinx expects ILA however these (starting at yellow line) are ADC converted samples, not ILA. 0x69000 = 0x80
      
     
     
     
     
     
     
     
     
     
     
     
     
     
     
     
     
     
     
     
     
     
     
     
     
     
     
     
     
     
     
     
     
     

  • Hi Jim,
    I attached a file with a complete description of my ILA problem. Previous post did not work. Thanks, John
  • John,

    When we use this setup with the VC707, we need to provide both the REF CLK and CORE CLK at the lane rate/10. This would be 307.2MHz. Can you try this with your hardware? Our design team also suggested using a high speed scope probe to see actually what is coming out of the ADC. Is this possible? I tried calling but got your voice mail. What time zone are you in?

    Regards,

    Jim 

  • Hi Jim,

    Thanks for your advice and suggestions.   Today, I have tried the following:

    From ADS54J60_LMF_8224.ini, I tried reversing (and not reversing) lanes 0-7 and also following the Bit Packing Channel Pattern

    \\ lane0:7 - lane 0 of ADC is going to lane 7 of capture card        

    Bit Packing Channel Pattern =C2S3[15:8],C2S3[7:0],C2S7[15:8],C2S7[7:0],
                                                    C2S2[15:8],C2S2[7:0],C2S6[15:8],C2S6[7:0],
                                                    C2S1[15:8],C2S1[7:0],C2S5[15:8],C2S5[7:0],
                                                    C2S4[15:8],C2S4[7:0],C2S8[15:8],C2S8[7:0],
                                                    C1S3[15:8],C1S3[7:0],C1S7[15:8],C1S7[7:0],
                                                    C1S2[15:8],C1S2[7:0],C1S6[15:8],C1S6[7:0],
                                                    C1S1[15:8],C1S1[7:0],C1S5[15:8],C1S5[7:0],
                                                    C1S4[15:8],C1S4[7:0],C1S8[15:8],C1S8[7:0]

    I also went through the other setups in ADS54J60_LMF_8224.ini and tried to align my AXI4 JESD PHY writes to them.

    Finally, I forced the ADS54J60 to subclass 0 by writing:  0 to 0x690007

    How can the core_clock be anything other than 76.8 MHz if each ADC has to deliver 8 samples/core_clock (614.4/8 = 76.8)?

    I am sure there is a (maybe undocumented) level at which 307.2MHz core_clock makes sense however I can't see it now.

    Also, according to the ADS54J60 data sheet, page 55, the ADC assumes 20X line rate. 
    Is X = the JESD GTX RefClk?  And that case RefClk has to be 153.6 MHz,

    Do you think the Xilinx JESD designers you work with would be willing to send me a Vivado project that just runs the ADS54J60 card?  Either Verilog or VHDL is OK.

    Thanks,

    John Reyland