the lmfs i use is 8224 , and the clock to adc is 500Mhz, the sine wave is 2MHz.
the sync is high . the fpga can receive data .
but the data is not standard sine wave .
the detail wave is fig below .
any body can give me ans suggestion
This thread has been locked.
If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.
the lmfs i use is 8224 , and the clock to adc is 500Mhz, the sine wave is 2MHz.
the sync is high . the fpga can receive data .
but the data is not standard sine wave .
the detail wave is fig below .
any body can give me ans suggestion
Hello Weibo,
Are you using the TI ADS54J60EVM or is this a custom board? If you are using the ADC GUI, can you send screen shots of all of the tabs? If not, can you send the register settings for the ADC? What part is used for clocking the ADC and FPGA/ASIC? If it is the LMK part from TI, please send the register settings for this part as well. I do not see a plot of the waveform, only a digital bus.
Regards,
Jim
Weibo,
When using subclass 0, the ADS54J60 still needs a SYSREF pulse to synchronize the internal clocks. This can be done in software as shown in the attachment. This will be added to the next revision of the data sheet.
Regards,
Jim
why do you haven not update the new revision of data sheet in the website. i set the register to synchronize the internal clocks . but some times ,i also can not get a standard sine wave . can you pass a whole new revision of the datasheet .
thanks your pdf. But , i still can not solve my question. i use ads54j60, lmfs is 8224 . and xilinx jesd204 ip .
i use debug to grasp adc data from jesd2034 ip . but some channels is not a smooth sine wave . sometimes , i reset the system , configure the adc once again. the waveform is normal , but sometimes, it's bad.
can you give me some suggestions .
Weibo,
Send me the entire ADC register file you are using and I will duplicate this with our setup just to make sure you are loading the ADC properly. Are you providing a pulse reset after loading all registers in page 0x6800? Are you writing to the master page rest as well as the digital reset on page 6800 address F7? Have you contacted Xilinx for help?
Regards,
Jim
Jim,
this is my register file. i havn't contact Xilinx .
0x0000 => 0x81;
0x0011 => 0x80;
0x0059 => 0x20;
0x8059 => 0x00(read the register)
0x4003 => 0x00;
0x4004 => 0x68;
0x60f7 => 0x01;
0x6000 => 0x01;
0x6000 => 0x00;
0xe000 => 0x00;
0x4003 => 0x00;
0x4004 => 0x69;
0x6000 => 0x80;
0x6007 => 0x00;
0x6005 => 0x80;
0x6006 => 0x0f;
0xe006 => 0x00;(read the register)
0x4003 => 0x00;
0x4004 => 0x6a;
0x6012 => 0x02;
0x7012 => 0x02;
0x0011 => 0x80;
0x0054 => 0x80;
0x0053 => 0x01;
0x0053 => 0x00;
0x0053 => 0x01;
0x0053 => 0x00;
thanks,
Weibo,
I tried your config file on our setup which uses an Altera Arria V, and had no problems getting valid data. I will try this next on our VC707 platform. Which version of Vivado are you using? What family of FPGA are you targeting?
Regards,
Jim