ADC32RF45 / about thermal information

Hi,

I will have to ask the design team if these thermal parameters in the datasheet are from a standard test board stackup such as the 4layer Jedec or from an assumption of a custom stackup.    It is probably the 4-layer Jedec board, as described in the datsheet link to http://www.ti.com/lit/an/spra953c/spra953c.pdf but I need to verify that.  It is not common to assume some other test board structure unless it is something that we can know in advance is common to a particular industry use case. 

For power consumption, the strongest parameter influencing power dissipation is sample rate;  lower sample rate leads to lower power dissipation.  The choice of digital mode of operation has less effect.  For example, from the datasheet the typ power dissipation at 3Gsps in bypass mode is 6.4W for two channels, while the same 3Gsps but with 8x decimation single DDC is also 6.4W for two channels.  (page 6 of the July revision datasheet on ti.com)  Turning on the second DDC for each channel brings the power dissipation to 6.7W.     

Regards,

Richard P.

Hi,

I checked with the design team, and the thermal parameters are done assuming the Jedec 4-layer board.

Regards,

Richard P,