AD16DV160: Balanced Differential Filter simulation in TINA

Hi Amit
I'm not sure about the problem in TINA, but it might be worth trying a single ended equivalent to the differential circuit. That way one end of the generator and load will be at ground which may suit the simulator better. If you can get results there it will help resolve the issue with the insertion loss using Elsie.
Most of our team is out for the US Thanksgiving holiday but if you're still having issues with this someone will be able to help early next week.
Best regards,
Jim B

Hello Jim B,

I can understand that the team is out of station.

No issues we will continue the discussion, as I have some more queries in this.

1) Regarding your reply - I am able to do balanced filter simulation in TINA (2nd figure)- by adding L & C impedances manually- by which Irregular circuit error can be removed . Where as same I followed for filter in figure 1- but  it is popping  an error. Is there something else that I need to look into for figure 1 above.

2)I think that 12 dB insertion loss (in the last figure) is because of filter topology - The inductor L = 6.85nH is in parallel with the output termination. which is giving voltage loss... well this need to be confirmed from your end.  

3) The document: snau079- specifies that this filter (shown below) insertion loss  is almost 0 dB.

In the snap below what is the filter topology used. What tools I can use for this filter design. As in Elsie or FilterFree tools I have not seen this topology.(LC arrangement).

If any app or other reference supporting this filter design is there, then kindly share with me.

4) Also in the snap, the filter termination is shown 100E on both the outputs,  which is 200E output termination for a filter.

Where as In ADC16DV160 data sheet It is mentioned that for better dynamic performance of the ADC the source impedance of the ADC driver has to be less than 100E.

Kindly clarify this ...

Regards,

Amit Prakash Jagtap

Hi Amit,

I am the amplifier applications engineer for the LMH6517. I will give you feedback shortly.

Regards,
Loren

Hi Amit,

I think the 12dB loss is an artifact of the simulator. When you provide input termination to the filter that adds another 6dB of loss in addition to the output termination.

When I am modeling filters I will set a voltage meter on the filter side of the input termination resistors. That voltage can then be used as the reference for the loss in the filter.

The filter in Figure 6 above has an impedance transform that enables less voltage loss. There is still power loss.

It is correct that the ADC works best with 100 Ohm or lower source impedance. The flip side is that the amplifier works best with 200 Ohm or higher load impedance. In order to get the best overall performance of the amplifier and ADC combined it is necessary to find the impedance that gives the best overall performance. This is usually around 200 Ohms since the amplifier loses performance faster than the ADC gains performance.

If you have additional questions feel free to post them here. I will receive email notification when you post because I am now subscribed to this thread.

Regards,
Loren

Hello Loren,

As you said,

1) I will put a voltmeter on the filter input side (after)  series termination resistors and will check the result.

And if the loss is 6 dB can I implement the same filter. I mean the practically, this artifacts effect will not be present. ...

-> Please confirm.

2) Thanks for great explanation of impedance trade off between Opamp and ADC and specially the last statement (This is usually around 200 Ohms since the amplifier loses performance faster than the ADC gains performance. ) ... I will keep this in mind...for future designs.

3) Form my last post..third point is still pending.... expecting reply for it...

[3) The document: snau079- specifies that this filter (shown below) insertion loss  is almost 0 dB.

In the snap below what is the filter topology used. What tools I can use for this filter design. As in Elsie or FilterFree tools I have not seen this topology.(LC arrangement).

If any app or other reference supporting this filter design is there, then kindly share with me.]

Regards,

Amit P Jagtap

Waiting for Support...

Hello Amit,

The claim of 0dB loss for the filter is based on voltage gain due to low impedance input and high impedance output.  This is voltage gain, but obviously not power gain.  This works only when the ADC can take a high impedance source (>100 Ohms).  The claim is an approximation based on the special case where the impedance transform completely cancels the termination losses.  This will require a lot of time with simulation to tune the circuit. 

It is best to do the initial design for the filter with 5% to 10% higher frequency.  Filters nearly always shift down in frequency response when built on a printed circuit board. 

I will attach a spreadsheet that will help with the filter design.  I am not aware of any filter design software that has completely automated this filter topology. 

Regards,

Loren

100ohm_tappedL_AAF.xlsx