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ADS54j60 no common-mode voltage on transceivers

Other Parts Discussed in Thread: ADS54J60

Hi !

I'm using two ADS54J60 on my prototype board.  The board has worked for 2 weeks flawlessly.  But now, one of the ADC is not working.  I've found out that all transceivers lanes on this ADC are stuck at 10mV.  The other transceiver lanes on the working ADC are 0.332VDC.  After the series capacitors on the JESD204B lanes on both ADC, the common-mode voltage is about 0.7VDC.  The ADC configuration seems to be valid, I can access the SPI registers.  All the power pins are at the nominal levels, the Vcm pin is at 2.1V.

I've checked the TSW54J60 evaluation board and the transceiver lanes are at 0.332VDC at boot-up without any FPGA or ADC configuration.

Is this ADC fried?

Thanks,

Patrice

  • Patrice,

    Did you check the level of the reset input to the bad ADC? Is the clock input valid as well? I will check with the design team regarding the CM level you are seeing. Are both ADC's receiving power from the same source? Is there chance some flux might be shorting out some pins on this part? Have you tried cleaning the board using an ultrasonic cleaner then baking the board?

    Regards,

    Jim

  • Jim,

    I did some progress on my side. I've verified the reset and the clock signal. I've discovered that on boot-up, both of my ADC's transceiver output will be set to 0.3VDC if it gets a valid device clock and the ADC is not programmed. You need to have a valid device clock in order to get the transceiver powering up. Also, it seems that when I program the bad ADC via SPI on my prototype board, the transceiver output is powering down.

    I've realized that the SPI interface to both ADCs was running at 5MHz but the max frequency in the datasheet is 2MHz. I will modified my firmware and try at 2MHz.

    Thanks,

    Patrice
  • Patrrice,

    The SPI will not work unless a device clock is present. We always program our LMK clock device first, do a hard ADC reset, then program the ADC. 

    Regards,

    Jim