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DAC38J84 DACPLL bypass not working properly

Javier Rodriguez91
Prodigy 150 points
Other Parts Discussed in Thread: DAC38J84

Hi,

I have been working with the DAC38J84 for some time and for a project I want to bypass the DACPLL. So I followed the datasheet steps as follows:

- reset_pll = 1, pll_sleep = 1

- enable_pll = 0

- serdes_clk_sel = 1

I am feeding the DACCLK input with 500MHz for a 500MSPS conversion rate. The JESD lines work at 5Gbps (8 lanes with 841 configuration and half-rate).

The input frequency at the SERDES PLL is also 500MHz with a MPY factor of 5, thus generating 2.5GHz at the output.

For some reason I can't make it work (the SERDES PLL doesn't lock). However if I use the internal DACPLL, everything is fine.

If I don't put the pll into sleep (pll_sleep = 0), I can get the SERDES PLL to lock, but the JESD links don't start up.

Am I missing anything??

Thanks in advance.

  • 0
    TI__Guru* 91947 points

    Javier,

    Are you using the TI DAC GUI to program the DAC? If so, please take a look at the attached screen shots of the GUI. Is this how your setup is? If not please let me know what needs to be changed so I can try and duplicate your setup.  Can you send the complete register settings you are using for the DAC and LMK (if you are using an LMK device).

    Regards,

    Jim 

    DAC38J84 PLL bypass.pptx

  • 0 in reply to jim s
    Prodigy 150 points

    Hi Jim,

    No I am not using the DAC GUI since every time I download and extract it I am missing 2 dlls. Besides the board I'm working with doesn't have any means to connect to a host computer through USB, which I think it's required for the GUI to properly work.

    Anyway, I found the solution for this problem. As I told you I was following the datasheet documentation and that's what is wrong. There is an error in the documentation. On page 26, Figure 53, the multiplexer that selects between the DAC PLL output clock and the DAC clock inputs is not defined properly. With 0, the multiplexer selects the external clock while using 1 selects the DAC PLL output. This is totally the opposite to what it shows in that figure. Furthermore, the register description doesn't clarify anything and the only significant information must be extracted from this figure, which is wrong.

    Please review and update your documentation or add some errata, so things like these can be avoided. I've been stuck with this for a week, and as you can imagine, debugging 5Gsps links isn't easy. You can't expect everyone to use the GUI for their personal development.

    Have a nice day :)