DAC34H84

Hi New2day,

The DAC34H84 (the DAC348x family) has been used by many of our customers in applications requiring multi-device synchronization. So far, we have not observed any issues. Most of the initial issues are due to sequencing of the clocks, OSTR, and configurations. Let's take a look at couple of key points to see if we can narrow down the cause:

Timing of the clock, OSTR, and ISTR

1. Briefly looking at this history, I see that you have taken care of all the timing requirements for the clock setup. I just want to emphasize again that it is very important that the clock distribution for the DAC devices must have precise alignment of DACCLK and OSTR. Multiple copies of DACCLK and OSTR must be precisely aligned to ensure the FIFO read pointer are read at the same time instance.

2. the data coming out of the FPGA must be send in the same order among multiple DAC devices. The order of the data is registered through the ISTR signal. The idea is that you must load the data in the same fashion, let the FIFO absorb the timing variation, and read back the FIFO at the same exact time instance.

Configuration:

1. Besides the FIFO read/write pointer setup in config 0x20, you must also enable the clock divider setup. Please ensure that the clock divider sync is enabled through config 0x00, bit 2. 

2. syncsel_fifoin(3:0) must be set as ISTR, and syncsel_fifoout must be set as OSTR. Please set clkdiv_sync_sel as OSTR as well. The clock divider for the internal logic must be synchronized at the FIFO output side through OSTR to ensure all logic latency are the same among multiple devices. They are located in config32, 0x20 register

3. syncsel_fifo_input must be set to 0x00 in 0x1F register. This ensures the routing of the LVDS ISTR external signal is routed correctly internally.

4. Is NCO or any of the DSP logics such as QMC enabled? If so, could you disable them temporarily to see if the baseband signal is being aligned correctly. The NCO and QMC requires additional steps to ensure the logics are initalized to achieve the same latency.

5. Is on-chip PLL enabled? If so, additional requirements on the PFD must be met. 

If you can share your start-up sequence + programming, I can take a look as well.

-Kang

Hi New2day,

new2day said:

One question, would ISTR have to be periodic signal if OSTR is periodic signal? Thanks.

No, not necessarily, as long as you can ensure that the initial ISTR signal would have the same deterministic latency (i.e. no change in delay) as the theoretical periodic ISTR. The problem with the initial ISTR is that the FPGA's state machine (depending on the firmware design) may change the characteristic of the overall FPGA timing when compared with the initial ISTR timing. This problem could potentially change the latency on the "normal" operation stage of the FPGA+DAC setup when compared with the initial latency setup. The advantage of continuous ISTR is that you can always be certain that the FIFO gets reset according the new timing information of each stage of FPGA timing. The disadvantage is perhaps you will see additional coupling of the ISTR modulated onto the DAC output in double side band modulation manner.

To help isolate your problem at this point, I propose to do the following:

Goal: to ensure everything after the FIFO output (i.e. all the DSP logics are in sync among multiple chips

Summary: send DC type signal at the FIFO input so the FIFO input timing is not time variant. Enable coarse mixer and NCO to ensure the OSTR timing to initialize the DSP logics are good to ensure output phase matching.

1. send a full-scale negative or positive signal (DC, static) through the LVDS bus by setting all 32-bit LVDS bus to be logic high or low (i.e. 0xFFFF or 0x0000).

2. change 2's complement bit in config2 to 1b'0 to set to offset binary. At this point, DC values from the FPGA will be full-scale to the DAC. data to the FIFO input is not time variant and remains constant.

3. Start the DAC as normal, provide DACCLK and OSTR to all DAC devices with same latency as normal.

4. Enable coarse mixer. Walk the coarse mixer setting from Fs/2, Fs/4, and to Fs/8. Compare the output of the channel A, B, C, and D among multiple DAC devices. The output should be phase aligned. 

a. config 2, bit 6 should be enabled to enable coarse mixer

b. config13, bit 15:12, set CMIX setting per table 8

c. note. If the FIFO output side and all the clock dividers are synchronized correctly by the DACCLK and OSTR, then the coarse mixer logic should be initialized as well without further tuning. If not, double check on the DACCLK to OSTR timing. Also double check on the clock divider initialization sequence.

5. repeat with NCO enabled. Make sure NCO is synchronized by the OSTR in config31, bit 7:4. NCO frequency cycle may be impacted by the periodicity of the OSTR, please check the app note for the periodicity requirement. Simply set to multiples of OSTR frequency to simplify the problem.

If both step 4 and step 5 are successful, then we need to narrow down the problem the FIFO input side. Once we narrowed it down, we can discuss further.