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DAC3283EVM: DAC3283 Communications

Part Number: DAC3283EVM
Other Parts Discussed in Thread: CDCE62005, DAC3283

I am trying to get the DAC3283EVM to work correctly with an Altera Cyclone V GT dev kit. I have what I believe is the correct interface, but I'm a little confused at the relationship between the DACCLK and the DATACLK. I've seen conflicting information and just want to make sure I'm doing everything correctly.

Using the default settings, the clock coming into the FPGA is 153.6MHz. The DACCLK is 614.4MHz. I use the 153.6MHz clock to generate a DDR output, essentially giving me an effective data rate of 307.2MHz. With the default interpolation of 2x is this correct?

We are trying to output a 10MHz sine/cosine waveform directly from the DAC, so I have made the adjustments according to the EVM guide in section 4.1.

  • Jason,

    Are you using the FRAME clock and OSTR? If so, what frequency are these running at? Keep in mind that the data input is 8 bits at a time and shared by both channels.  I am working on creating a duplicate setup to verify yours. Are you also using the TSW1400EVM?

    Regards,

    Jim  

  • I am not using the TSW1400EVM, instead I'm using the Altera Cyclone V GT Development Kit. I am using the frame clock as described in the data sheet. It says to output the rising edge every 8 samples, which I equated to 16 clock cycles as there are 2 clock cycles per a sample of I and Q data. I also tested the IO pattern checker using a static pattern and I didn't see any errors. At this point I just want to make sure I have the settings right on the EVM to produce the correct outputs.

  • Jason,

    I got your setup to work with the following settings:

    FIFO OSTR = 38.4MHZ

    FPGA CLK = 153.6MHz

    DACCLK = 614.4MHz

    FIFO ISTR = 38.4MHz

    DATACLK = 307.2Msps   (614.4Msps DDR, 1 sample of I and Q)

    int = 4x

    If int = 2x, DATACLK = 614.4Msps which exceeds the data sheet limit of 312.5Msps.

    Regards,

    Jim

  • I have adjusted the FPGA to produce the DATACLK and FRAMECLK at the revised frequencies. Are there any other settings I need to adjust in the DAC3283EVM program besides the frequencies and the interpolation to 4x instead of 2x?

  • Jason,

    No. The settings used by the DAC GUI are shown in attachment.

    Regards,

    Jim

    DAC3282_LO_2p4G.pptx

  • It looks like the interpolation is set to 1 in the slides you sent. That is different then the 4x you said earlier. Am I interpreting this correctly?

    Also, I'm looking at evaluating a sinewave at 10MHz synthesized directly from the FPGA. I'm not using the TRF3720. I moved the resistors to output the analog channels of the DAC on J3 and J1. Unfortunately, I'm seeing a distorted waveform. I attached an output of Modelsim showing the DAC DATACLK, FRAMECLK, and DATA with the frequencies you listed earlier. Does that look correct?

  • Jason,

    The screen shot had a typo. It was suppose to be set to 4X interpolation. I bypassed the modulator and sent the signal to the transformer and verified I get a nice clean 10MHz output using the setups I sent. The TSW1400EVM is sending a DATACLK at 614.4MHz and the FRAME CLK is at 38.4MHz. Yoiur post did not send any of the waveforms you mention for me to look at.

    Regards,

    Jim 

  • I have attached an image of the waveform above. The 1st signal is channel I, the 2nd signal is channel Q, the third signal is the DATACLK from the FPGA to the DAC. The 4th signal is the FRAMECLK from the FPGA to the DAC, and the 5th signal is the DATA from the FPGA to the DAC.

  • Jason,

    The signals above look fine with respect to the edges and the period relationship between FRAMECLK and DATACLK. Since the input data is DDR and you are using 2X int, if the data was 16 bits and non-interleaved, the DATACLK from the FPGA would be 153.6MHz. But since the data is only 8 bits and interleaved, the DATACLK needs to be 614.4Msps. 

    Regards,

    Jim 

  • Ok, I'm again being confused at the frequency and interpolation settings I should use based on your previous posts.


    The model waveform I posted was with the following settings


    Interpolation = 4x From DAC MENU

    DACCLK = 614.4 From CDCE62005

    FIFO_OSTR_CLK = 38.4MHz From CDCE62005

    DATACLK = 307.2 MHZ From FPGA (DDR = 614.4 equivalent rate)

    FRAMECLK = 19.2MHz From FPGA (this is rising edge to rising edge which gives 8 samples of I and Q data. I don't understand how this could be 38.4MHz and still get 8 samples of data with a 307.2MHz DATACLK)

    I took this data from the initial post where you told me the settings to use. You said to use 4x interpolation because 2x wasn't possible with the clock rate limitation on the FPGA. That being said I don't understand the FRAMECLK frequency rate with respect to the data sheet asking for 8 samples. With a DATACLK of 307.2MHz, this comes out to 19.2MHz, which can be seen in the previous waveform I posted.

    In your latest post you mention an interpolation rate of 2x, but you previously said that was not possible with the FPGA clock limitation. What do I need to change in the above setup to have correct values?

  • Also, I had another question. When I program the FPGA with the DAC code I see a distorted waveform appear on the output at J3, before programming it is relatively flat. When I power the FPGA board off, the waveform output still persists. Is this some artifact of losing the DATACLK that causes the DAC output to hold the last value, or is this noise or something?

  • Hi Jason,

    I’m going to try and replicate your setup in the lab, and determine what you would need to change, if anything. I will also look into the matter of the distorted waveform at J3 as well.

    Regards,

    Abdallah
  • I suspect that the coarse mixer on the DAC3283 was still running and it is causing the output waveform to appear on J3. The final input on your FPGA may be latching in instead of shutting off after completing its transmission. Any remaining DC value mixed with the coarse mixer will produce a tone at the output.

  • DATACLK is the rate at which the DAC is taking in the data. The effective data rate*interpolation is the rate at which the DAC is creating the analog signal.  For your individual case you have 2 channels, I assume a data rate of 153.6MHz and a resolution of 16 bits/sec, then the rate at which DATACLK must operate is then (2*153.6*16)/(8*2) = 307.2MHz.

    DACCLK is the sampling clock of the DAC and the rate at which the DAC outputs the data.

    I replicated your setup on the bench, and am still looking into the matter of the distorted waveform you reported on J3, could you send me a screenshot? Could you also send me a register dump so that I may review?

  • saved_registers.txt
    Texas Instruments Inc.
    DAC32x2 EVM Register Configuration
    
    DAC32x2 Registers
    Address	Data
    00		70
    01		21
    02		00
    03		10
    04		FF
    05		30
    06		00
    07		20
    08		B7
    09		7A
    0A		B6
    0B		EA
    0C		45
    0D		1A
    0E		16
    0F		AA
    10		C6
    11		24
    12		02
    13		00
    14		00
    15		00
    16		00
    17		00
    18		83
    19		00
    1A		00
    1B		00
    1C		00
    1D		00
    1E		24
    1F		12
    20		00
    21		00
    
    CDCE62005 Registers
    Freq:19.200000MHz
    Address	Data
    00		01040300
    01		81400321
    02		81840302
    03		81840303
    04		01040304
    05		381C0A85
    06		04BE1F26
    07		3D98F7F7
    08		20001808
    <Cluster>
    <Name></Name>
    <NumElts>9</NumElts>
    <Cluster>
    <Name>Freq Calculations</Name>
    <NumElts>6</NumElts>
    <EXT>
    <Name>VCO Freq Actual[MHz]</Name>
    <Val>2400.00000</Val>
    </EXT>
    <EXT>
    <Name>RF Freq Actual[MHz]</Name>
    <Val>2400.00000</Val>
    </EXT>
    <EXT>
    <Name>PFD Freq Actual[MHz]</Name>
    <Val>0.80000</Val>
    </EXT>
    <DBL>
    <Name>RF Stepsize [MHz]</Name>
    <Val>0.80000</Val>
    </DBL>
    <DBL>
    <Name>Fraction [KHz]</Name>
    <Val>0.00000</Val>
    </DBL>
    <DBL>
    <Name>CAL_CLK_FREQ [MHz]</Name>
    <Val>5.00000E-2</Val>
    </DBL>
    </Cluster>
    <Cluster>
    <Name>Freq Targets</Name>
    <NumElts>5</NumElts>
    <DBL>
    <Name>Ref Freq[MHz]</Name>
    <Val>76.80000</Val>
    </DBL>
    <EXT>
    <Name>RF Target [MHz]</Name>
    <Val>2400.00000</Val>
    </EXT>
    <DBL>
    <Name>INT Step (MHz)</Name>
    <Val>0.80000</Val>
    </DBL>
    <I8>
    <Name>Int/Frac Select</Name>
    <Val>0</Val>
    </I8>
    <Boolean>
    <Name>stop</Name>
    <Val>1</Val>
    </Boolean>
    </Cluster>
    <Cluster>
    <Name>Reg1</Name>
    <NumElts>9</NumElts>
    <I8>
    <Name>ADDR</Name>
    <Val>9</Val>
    </I8>
    <I16>
    <Name>RDIV</Name>
    <Val>96</Val>
    </I16>
    <I8>
    <Name>RSV</Name>
    <Val>0</Val>
    </I8>
    <I8>
    <Name>REF_INV</Name>
    <Val>0</Val>
    </I8>
    <I8>
    <Name>NEG_VCO</Name>
    <Val>1</Val>
    </I8>
    <I8>
    <Name>ICP</Name>
    <Val>0</Val>
    </I8>
    <I8>
    <Name>ICPDOUBLE</Name>
    <Val>0</Val>
    </I8>
    <I16>
    <Name>CAL_CLK_SEL</Name>
    <Val>12</Val>
    </I16>
    <I8>
    <Name>RSV 2</Name>
    <Val>0</Val>
    </I8>
    </Cluster>
    <Cluster>
    <Name>Reg2</Name>
    <NumElts>9</NumElts>
    <I8>
    <Name>ADDR</Name>
    <Val>10</Val>
    </I8>
    <U16>
    <Name>NINT</Name>
    <Val>3000</Val>
    </U16>
    <I8>
    <Name>PLL_DIV_SEL</Name>
    <Val>0</Val>
    </I8>
    <I8>
    <Name>PRSC_SEL</Name>
    <Val>1</Val>
    </I8>
    <I8>
    <Name>RSV</Name>
    <Val>0</Val>
    </I8>
    <I8>
    <Name>VCO_SEL</Name>
    <Val>2</Val>
    </I8>
    <I8>
    <Name>VCOSEL_MODE</Name>
    <Val>0</Val>
    </I8>
    <I8>
    <Name>CAL_ACC</Name>
    <Val>0</Val>
    </I8>
    <I8>
    <Name>EN_CAL</Name>
    <Val>0</Val>
    </I8>
    </Cluster>
    <Cluster>
    <Name>Reg3</Name>
    <NumElts>3</NumElts>
    <I8>
    <Name>ADDR</Name>
    <Val>11</Val>
    </I8>
    <U32>
    <Name>NFRAC</Name>
    <Val>0</Val>
    </U32>
    <I8>
    <Name>RSV</Name>
    <Val>0</Val>
    </I8>
    </Cluster>
    <Cluster>
    <Name>Reg4</Name>
    <NumElts>25</NumElts>
    <I8>
    <Name>ADDR</Name>
    <Val>12</Val>
    </I8>
    <I8>
    <Name>PWD_PLL</Name>
    <Val>0</Val>
    </I8>
    <I8>
    <Name>PWD_CP</Name>
    <Val>0</Val>
    </I8>
    <I8>
    <Name>PWD_VCO</Name>
    <Val>0</Val>
    </I8>
    <I8>
    <Name>PWD_VCOMUX</Name>
    <Val>0</Val>
    </I8>
    <I8>
    <Name>PWD_DIV124</Name>
    <Val>0</Val>
    </I8>
    <I8>
    <Name>PWD_PRESC</Name>
    <Val>0</Val>
    </I8>
    <I8>
    <Name>PWD_RESYNC</Name>
    <Val>0</Val>
    </I8>
    <I8>
    <Name>PWD_OUT_BUFF</Name>
    <Val>1</Val>
    </I8>
    <I8>
    <Name>PWD_LO_DIV</Name>
    <Val>1</Val>
    </I8>
    <I8>
    <Name>PWD_TX_DIV</Name>
    <Val>0</Val>
    </I8>
    <I8>
    <Name>PWD_BB_VCM</Name>
    <Val>0</Val>
    </I8>
    <I8>
    <Name>PWD_DC_OFF</Name>
    <Val>0</Val>
    </I8>
    <I8>
    <Name>EN_EXTVCO</Name>
    <Val>0</Val>
    </I8>
    <I8>
    <Name>EN_ISOURCE</Name>
    <Val>0</Val>
    </I8>
    <I8>
    <Name>LD_ANA_PREC0</Name>
    <Val>0</Val>
    </I8>
    <I8>
    <Name>LD_ANA_PREC1</Name>
    <Val>0</Val>
    </I8>
    <I8>
    <Name>CP_TRISTATE</Name>
    <Val>0</Val>
    </I8>
    <I8>
    <Name>SPEEDUP</Name>
    <Val>0</Val>
    </I8>
    <I8>
    <Name>LD_DIG_PREC</Name>
    <Val>0</Val>
    </I8>
    <I8>
    <Name>EN_DITH</Name>
    <Val>1</Val>
    </I8>
    <I8>
    <Name>MOD_ORD</Name>
    <Val>2</Val>
    </I8>
    <I8>
    <Name>DITH_SEL</Name>
    <Val>0</Val>
    </I8>
    <I8>
    <Name>DEL_SD_CLK</Name>
    <Val>2</Val>
    </I8>
    <I8>
    <Name>EN_FRAC</Name>
    <Val>0</Val>
    </I8>
    </Cluster>
    <Cluster>
    <Name>Reg5</Name>
    <NumElts>14</NumElts>
    <I8>
    <Name>ADDR</Name>
    <Val>13</Val>
    </I8>
    <I8>
    <Name>VCOBIAS_RTRIM</Name>
    <Val>4</Val>
    </I8>
    <I8>
    <Name>PLLBIAS_RTRIM</Name>
    <Val>2</Val>
    </I8>
    <I8>
    <Name>VCO_BIAS</Name>
    <Val>8</Val>
    </I8>
    <I8>
    <Name>VCOBUF_BIAS</Name>
    <Val>2</Val>
    </I8>
    <I8>
    <Name>VCOMUX_BIAS</Name>
    <Val>3</Val>
    </I8>
    <I8>
    <Name>BUFOUT_BIAS</Name>
    <Val>0</Val>
    </I8>
    <I8>
    <Name>RSV</Name>
    <Val>0</Val>
    </I8>
    <I8>
    <Name>VCO_CAL_IB</Name>
    <Val>0</Val>
    </I8>
    <I8>
    <Name>VCO_CAL_REF</Name>
    <Val>2</Val>
    </I8>
    <I8>
    <Name>VCO_AMPL_CTRL</Name>
    <Val>3</Val>
    </I8>
    <I8>
    <Name>VCO_VB_CTRL</Name>
    <Val>0</Val>
    </I8>
    <I8>
    <Name>VCO_MUX_GAIN</Name>
    <Val>0</Val>
    </I8>
    <I8>
    <Name>EN_LD_ISOURCE</Name>
    <Val>0</Val>
    </I8>
    </Cluster>
    <Cluster>
    <Name>Reg6</Name>
    <NumElts>8</NumElts>
    <I8>
    <Name>ADDR</Name>
    <Val>14</Val>
    </I8>
    <I16>
    <Name>IOFF</Name>
    <Val>128</Val>
    </I16>
    <I16>
    <Name>QOFF</Name>
    <Val>128</Val>
    </I16>
    <I8>
    <Name>VREF_SEL</Name>
    <Val>4</Val>
    </I8>
    <I8>
    <Name>TX_DIV_SEL</Name>
    <Val>0</Val>
    </I8>
    <I8>
    <Name>LO_DIV_SEL</Name>
    <Val>0</Val>
    </I8>
    <I8>
    <Name>TX_DIV_BIAS</Name>
    <Val>1</Val>
    </I8>
    <I8>
    <Name>LO_DIV_BIAS</Name>
    <Val>2</Val>
    </I8>
    </Cluster>
    <Cluster>
    <Name>Reg7</Name>
    <NumElts>14</NumElts>
    <I8>
    <Name>ADDR</Name>
    <Val>15</Val>
    </I8>
    <I8>
    <Name>RSV</Name>
    <Val>0</Val>
    </I8>
    <I16>
    <Name>VCO_TRIM</Name>
    <Val>32</Val>
    </I16>
    <I8>
    <Name>RSV 2</Name>
    <Val>0</Val>
    </I8>
    <I8>
    <Name>VCO_TESTMODE</Name>
    <Val>0</Val>
    </I8>
    <I8>
    <Name>CAL_BYPASS</Name>
    <Val>0</Val>
    </I8>
    <I8>
    <Name>MUX_CTRL</Name>
    <Val>1</Val>
    </I8>
    <I8>
    <Name>ISOURCE_SINK</Name>
    <Val>0</Val>
    </I8>
    <I8>
    <Name>ISOURCE_TRIM</Name>
    <Val>4</Val>
    </I8>
    <I8>
    <Name>PD_TC</Name>
    <Val>0</Val>
    </I8>
    <I8>
    <Name>IB_VCM_SEL</Name>
    <Val>0</Val>
    </I8>
    <I8>
    <Name>MIXLO_VCM</Name>
    <Val>4</Val>
    </I8>
    <I8>
    <Name>DCOFFSET_I</Name>
    <Val>2</Val>
    </I8>
    <I8>
    <Name>VCO_TRIM_SEL</Name>
    <Val>1</Val>
    </I8>
    </Cluster>
    </Cluster>
    

  • In this case If I'm using the output as a control value. How would I properly make the output go back to 0? If shutting off the FPGA leaves that tone, which is producing a non-zero output, it could be bad for my system. I want to make sure the DAC output is 0 if I'm not sending it any data.

  • I think that what you would need to do is utilize the DATACLK monitor circuit. This circuit uses a counter that is reset on the rising edge of DATACLK, when DATACLK isn’t detected for four cycles, two errors are flagged and tx_off disables the DAC output. The details for setting this up can be found in the DAC3283 datasheet, specifically in section 8.4.8, on pages 26 and 27. Let me know if setting this up eliminates the distorted output on J3 or if you need help setting it up.

  • Are you still having problems or did the DATACLK monitor circuit eliminate the distorted waveform?
  • The clock monitor circuit seems to be working correctly for turning off the output. I'm not a huge fan of having to actively handle the reset to re-enable the DAC, but this should be a rare case so it's not the end of the world.

    The distorted waveform is still being produced though when I am actively running the DAC. Did you take a look at the register file I attached previously? Does it look like everything is setup correctly?

  • I did look at the register file, and didn't notice anything that was out of place. 

  • So I was able to get some waveforms working but I still have some questions. I have attached the pictures. Both waveforms were generated using the following settings:

    DACCLK = 614 MHz

    DATACLK = 307 MHz

    FRAMECLK = 19.2MHz

    OSTR = 19.2 MHz

    Interpolation = 4x

    Mixer = Bypass


    For testing, I am sending to the DAC a Sine and Cosine waveform generated from a 12-bit look up table. The last 4 bits are set to 0.

    They both show a 2.5MH sinewave. I do have some issues though. The first waveform is with the FIFO enabled. It clearly shows a distorted waveform. The first thing I did was check to see if the FIFO collision alarm was set. It was not. So there is no FIFO error and the waveform is looking distorted. The second waveform is much clearer. It is with the FIFO disabled. I'm assuming the spikes are due to the frequency being lower than the cut-off of the transformer. I don't  understand why the FIFO isn't working.

    Also, it might be an error on my end, but according to my calculations and modelsim, the waveform generator should have been producing a 5 Mhz signal. Instead I am seeing a 2.5MHz signal on the scope. Do you have any advice on the issues I'm seeing?

  • Hi Jason,

    I think you'd see a decrease in amplitude if it was the transformer rather than the distortions. I suspect a timing issue, or that the data isn't correct. I'm going to take a closer look at the register file you sent me. 

    Regards,

    Abdallah

  • Hi Jason,

    After looking into your register file again, it looks like you have the DAC fir0_ena set high, but you don’t have fir1_ena set high. Both have to be set high to enable x4 interpolation. You should change the value in CONFIG1, Address 0x01 from 21 to 31. This allowed me to produce the sine wave on my end without distortion, using your register values. Also, I think you should verify that your OSTR freq is correct. It should be, according to the datasheet the fDAC/(interpolation x 8) at a minimum, whereas your OSTR seemed to be set at 153.6 MHz.

    Regards,

    Abdallah

  • The following register file was used to create the waveforms I previously attached.

    savereg.txt
    Texas Instruments Inc.
    DAC32x2 EVM Register Configuration
    
    DAC32x2 Registers
    Address	Data
    00		30
    01		31
    02		00
    03		10
    04		FF
    05		30
    06		00
    07		20
    08		F5
    09		7A
    0A		B6
    0B		EA
    0C		45
    0D		1A
    0E		16
    0F		AA
    10		C6
    11		24
    12		02
    13		00
    14		00
    15		00
    16		00
    17		00
    18		80
    19		00
    1A		00
    1B		00
    1C		00
    1D		00
    1E		24
    1F		12
    20		00
    21		00
    
    CDCE62005 Registers
    Freq:19.200000MHz
    Address	Data
    00		01040300
    01		81400321
    02		811C0302
    03		81040303
    04		01040304
    05		381C0A85
    06		04BE1F26
    07		3D98F7F7
    08		20001808
    <Cluster>
    <Name></Name>
    <NumElts>9</NumElts>
    <Cluster>
    <Name>Freq Calculations</Name>
    <NumElts>6</NumElts>
    <EXT>
    <Name>VCO Freq Actual[MHz]</Name>
    <Val>2408.00000</Val>
    </EXT>
    <EXT>
    <Name>RF Freq Actual[MHz]</Name>
    <Val>2408.00000</Val>
    </EXT>
    <EXT>
    <Name>PFD Freq Actual[MHz]</Name>
    <Val>0.80000</Val>
    </EXT>
    <DBL>
    <Name>RF Stepsize [MHz]</Name>
    <Val>0.80000</Val>
    </DBL>
    <DBL>
    <Name>Fraction [KHz]</Name>
    <Val>0.00000</Val>
    </DBL>
    <DBL>
    <Name>CAL_CLK_FREQ [MHz]</Name>
    <Val>5.00000E-2</Val>
    </DBL>
    </Cluster>
    <Cluster>
    <Name>Freq Targets</Name>
    <NumElts>5</NumElts>
    <DBL>
    <Name>Ref Freq[MHz]</Name>
    <Val>76.80000</Val>
    </DBL>
    <EXT>
    <Name>RF Target [MHz]</Name>
    <Val>2408.00000</Val>
    </EXT>
    <DBL>
    <Name>INT Step (MHz)</Name>
    <Val>0.80000</Val>
    </DBL>
    <I8>
    <Name>Int/Frac Select</Name>
    <Val>0</Val>
    </I8>
    <Boolean>
    <Name>stop</Name>
    <Val>1</Val>
    </Boolean>
    </Cluster>
    <Cluster>
    <Name>Reg1</Name>
    <NumElts>9</NumElts>
    <I8>
    <Name>ADDR</Name>
    <Val>9</Val>
    </I8>
    <I16>
    <Name>RDIV</Name>
    <Val>96</Val>
    </I16>
    <I8>
    <Name>RSV</Name>
    <Val>0</Val>
    </I8>
    <I8>
    <Name>REF_INV</Name>
    <Val>0</Val>
    </I8>
    <I8>
    <Name>NEG_VCO</Name>
    <Val>1</Val>
    </I8>
    <I8>
    <Name>ICP</Name>
    <Val>0</Val>
    </I8>
    <I8>
    <Name>ICPDOUBLE</Name>
    <Val>0</Val>
    </I8>
    <I16>
    <Name>CAL_CLK_SEL</Name>
    <Val>12</Val>
    </I16>
    <I8>
    <Name>RSV 2</Name>
    <Val>0</Val>
    </I8>
    </Cluster>
    <Cluster>
    <Name>Reg2</Name>
    <NumElts>9</NumElts>
    <I8>
    <Name>ADDR</Name>
    <Val>10</Val>
    </I8>
    <U16>
    <Name>NINT</Name>
    <Val>3010</Val>
    </U16>
    <I8>
    <Name>PLL_DIV_SEL</Name>
    <Val>0</Val>
    </I8>
    <I8>
    <Name>PRSC_SEL</Name>
    <Val>1</Val>
    </I8>
    <I8>
    <Name>RSV</Name>
    <Val>0</Val>
    </I8>
    <I8>
    <Name>VCO_SEL</Name>
    <Val>2</Val>
    </I8>
    <I8>
    <Name>VCOSEL_MODE</Name>
    <Val>0</Val>
    </I8>
    <I8>
    <Name>CAL_ACC</Name>
    <Val>0</Val>
    </I8>
    <I8>
    <Name>EN_CAL</Name>
    <Val>0</Val>
    </I8>
    </Cluster>
    <Cluster>
    <Name>Reg3</Name>
    <NumElts>3</NumElts>
    <I8>
    <Name>ADDR</Name>
    <Val>11</Val>
    </I8>
    <U32>
    <Name>NFRAC</Name>
    <Val>0</Val>
    </U32>
    <I8>
    <Name>RSV</Name>
    <Val>0</Val>
    </I8>
    </Cluster>
    <Cluster>
    <Name>Reg4</Name>
    <NumElts>25</NumElts>
    <I8>
    <Name>ADDR</Name>
    <Val>12</Val>
    </I8>
    <I8>
    <Name>PWD_PLL</Name>
    <Val>0</Val>
    </I8>
    <I8>
    <Name>PWD_CP</Name>
    <Val>0</Val>
    </I8>
    <I8>
    <Name>PWD_VCO</Name>
    <Val>0</Val>
    </I8>
    <I8>
    <Name>PWD_VCOMUX</Name>
    <Val>0</Val>
    </I8>
    <I8>
    <Name>PWD_DIV124</Name>
    <Val>0</Val>
    </I8>
    <I8>
    <Name>PWD_PRESC</Name>
    <Val>0</Val>
    </I8>
    <I8>
    <Name>PWD_RESYNC</Name>
    <Val>0</Val>
    </I8>
    <I8>
    <Name>PWD_OUT_BUFF</Name>
    <Val>1</Val>
    </I8>
    <I8>
    <Name>PWD_LO_DIV</Name>
    <Val>1</Val>
    </I8>
    <I8>
    <Name>PWD_TX_DIV</Name>
    <Val>0</Val>
    </I8>
    <I8>
    <Name>PWD_BB_VCM</Name>
    <Val>0</Val>
    </I8>
    <I8>
    <Name>PWD_DC_OFF</Name>
    <Val>0</Val>
    </I8>
    <I8>
    <Name>EN_EXTVCO</Name>
    <Val>0</Val>
    </I8>
    <I8>
    <Name>EN_ISOURCE</Name>
    <Val>0</Val>
    </I8>
    <I8>
    <Name>LD_ANA_PREC0</Name>
    <Val>0</Val>
    </I8>
    <I8>
    <Name>LD_ANA_PREC1</Name>
    <Val>0</Val>
    </I8>
    <I8>
    <Name>CP_TRISTATE</Name>
    <Val>0</Val>
    </I8>
    <I8>
    <Name>SPEEDUP</Name>
    <Val>0</Val>
    </I8>
    <I8>
    <Name>LD_DIG_PREC</Name>
    <Val>0</Val>
    </I8>
    <I8>
    <Name>EN_DITH</Name>
    <Val>1</Val>
    </I8>
    <I8>
    <Name>MOD_ORD</Name>
    <Val>2</Val>
    </I8>
    <I8>
    <Name>DITH_SEL</Name>
    <Val>0</Val>
    </I8>
    <I8>
    <Name>DEL_SD_CLK</Name>
    <Val>2</Val>
    </I8>
    <I8>
    <Name>EN_FRAC</Name>
    <Val>0</Val>
    </I8>
    </Cluster>
    <Cluster>
    <Name>Reg5</Name>
    <NumElts>14</NumElts>
    <I8>
    <Name>ADDR</Name>
    <Val>13</Val>
    </I8>
    <I8>
    <Name>VCOBIAS_RTRIM</Name>
    <Val>4</Val>
    </I8>
    <I8>
    <Name>PLLBIAS_RTRIM</Name>
    <Val>2</Val>
    </I8>
    <I8>
    <Name>VCO_BIAS</Name>
    <Val>8</Val>
    </I8>
    <I8>
    <Name>VCOBUF_BIAS</Name>
    <Val>2</Val>
    </I8>
    <I8>
    <Name>VCOMUX_BIAS</Name>
    <Val>3</Val>
    </I8>
    <I8>
    <Name>BUFOUT_BIAS</Name>
    <Val>0</Val>
    </I8>
    <I8>
    <Name>RSV</Name>
    <Val>0</Val>
    </I8>
    <I8>
    <Name>VCO_CAL_IB</Name>
    <Val>0</Val>
    </I8>
    <I8>
    <Name>VCO_CAL_REF</Name>
    <Val>2</Val>
    </I8>
    <I8>
    <Name>VCO_AMPL_CTRL</Name>
    <Val>3</Val>
    </I8>
    <I8>
    <Name>VCO_VB_CTRL</Name>
    <Val>0</Val>
    </I8>
    <I8>
    <Name>VCO_MUX_GAIN</Name>
    <Val>0</Val>
    </I8>
    <I8>
    <Name>EN_LD_ISOURCE</Name>
    <Val>0</Val>
    </I8>
    </Cluster>
    <Cluster>
    <Name>Reg6</Name>
    <NumElts>8</NumElts>
    <I8>
    <Name>ADDR</Name>
    <Val>14</Val>
    </I8>
    <I16>
    <Name>IOFF</Name>
    <Val>128</Val>
    </I16>
    <I16>
    <Name>QOFF</Name>
    <Val>128</Val>
    </I16>
    <I8>
    <Name>VREF_SEL</Name>
    <Val>4</Val>
    </I8>
    <I8>
    <Name>TX_DIV_SEL</Name>
    <Val>0</Val>
    </I8>
    <I8>
    <Name>LO_DIV_SEL</Name>
    <Val>0</Val>
    </I8>
    <I8>
    <Name>TX_DIV_BIAS</Name>
    <Val>1</Val>
    </I8>
    <I8>
    <Name>LO_DIV_BIAS</Name>
    <Val>2</Val>
    </I8>
    </Cluster>
    <Cluster>
    <Name>Reg7</Name>
    <NumElts>14</NumElts>
    <I8>
    <Name>ADDR</Name>
    <Val>15</Val>
    </I8>
    <I8>
    <Name>RSV</Name>
    <Val>0</Val>
    </I8>
    <I16>
    <Name>VCO_TRIM</Name>
    <Val>32</Val>
    </I16>
    <I8>
    <Name>RSV 2</Name>
    <Val>0</Val>
    </I8>
    <I8>
    <Name>VCO_TESTMODE</Name>
    <Val>0</Val>
    </I8>
    <I8>
    <Name>CAL_BYPASS</Name>
    <Val>0</Val>
    </I8>
    <I8>
    <Name>MUX_CTRL</Name>
    <Val>1</Val>
    </I8>
    <I8>
    <Name>ISOURCE_SINK</Name>
    <Val>0</Val>
    </I8>
    <I8>
    <Name>ISOURCE_TRIM</Name>
    <Val>4</Val>
    </I8>
    <I8>
    <Name>PD_TC</Name>
    <Val>0</Val>
    </I8>
    <I8>
    <Name>IB_VCM_SEL</Name>
    <Val>0</Val>
    </I8>
    <I8>
    <Name>MIXLO_VCM</Name>
    <Val>4</Val>
    </I8>
    <I8>
    <Name>DCOFFSET_I</Name>
    <Val>2</Val>
    </I8>
    <I8>
    <Name>VCO_TRIM_SEL</Name>
    <Val>1</Val>
    </I8>
    </Cluster>
    </Cluster>
    

  • When doing the IO test, what is the recommended method for reseting everything? I click the little radio buttons but it takes forever to reset them.
  • In general, having both channels 180 degrees apart may indicate that the P/N pins for one of the channels may have been swapped. However in this case the IO test is used to check the LVDS data bus and the output during the test isn’t necessarily of any significance. Any valid alarms found would be the main concern. From your screenshot, it also looks like you have the FIFO disabled as well.

  • Yes, I disabled the FIFO because with it enabled, it caused the waveform to be more distorted.

    As far as the waveform I attached, I am outputting two positive numbers 0x1fff and 3fff on channel A and  issuing the frame after every two samples. (The intent was to use this setup for the IO test but noticed this wierd issue). Both of these values are positive. When I look at the scope I see a sine wave that goes positive and negative. If I am only outputting two positive values, essentially a square wave, then why am I seeing negative values?

    Also I output the same thing on channel B and get the same waveform but shifted 180 degrees. I don't see how it can be an issue with the pins reversed because I am using the dev kit. The FPGA pins are directly connected using the positive pins only and the negative pair is automatically created. There is nothing for the user to mess up. On the analog side, I am hooked up directly to J3 and J1. They are labelled as IOUTB2 and IOUTA2. Is there some internal DAC function that is shifting the waveform?


  • Ok, so I loaded your latest register values and enabled the FIFO. The distortion should disappear when you disable the Clock Divider Sync. This should only be enabled at startup and then disabled, or just disable it completely. Try that and let me know if you still observe distortion at the output when the FIFO is enabled.