Other Parts Discussed in Thread: CDCE62005, DAC3283
I am trying to get the DAC3283EVM to work correctly with an Altera Cyclone V GT dev kit. I have what I believe is the correct interface, but I'm a little confused at the relationship between the DACCLK and the DATACLK. I've seen conflicting information and just want to make sure I'm doing everything correctly.
Using the default settings, the clock coming into the FPGA is 153.6MHz. The DACCLK is 614.4MHz. I use the 153.6MHz clock to generate a DDR output, essentially giving me an effective data rate of 307.2MHz. With the default interpolation of 2x is this correct?
We are trying to output a 10MHz sine/cosine waveform directly from the DAC, so I have made the adjustments according to the EVM guide in section 4.1.