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ADC32RF45: The variation for Propagation delay time (tpd)

Hiroshi Katsunaga
Mastermind 6480 points
Part Number: ADC32RF45

Hello,

My customer has a question about ADC32RF45/80.

[Q]

Please tell me the variation for propagation delay time (tpd).

Do you have any data ?

Best Regards,

Hiroshi Katsunaga

  • 0
    TI__Mastermind 29220 points

    Hi,

    Are you asking for the min to max specification for tpd, which is only specified as typical 6ns?   I do not have that information.  I can ask the design team if they have that information, but it may not have been characterized.  Since the JESD204b format means that the receiving device has to lock onto the serialized data stream and establish a JESD204b link, and if multiple ADCs are in use and need to be synchronized then the JESD204b subclass1 method of using SYSREF to establish deterministic latency is used, and minor variations in tpd from device to device would have the same effect as minor routing mismatches in the serial lines themselves.  And these variations *are* what the JESD204b logic at the receiving end will dial out by setting the buffer release points to equalize overall latency across all such links.

    I will ask the design team if they have min and max specifications for this parameter.

    Regards,

    Richard P.

  • 0 in reply to Richard Prentice
    Mastermind 6480 points
    Hi Richard,

    Thank you for your fast response.

    Yes, they are asking for the min to max value for tpd, which is only specified as typical 6ns.
    I understand the values may not have been characterized.
    Therefore it's OK if you can provide it as the reference values.

    My understanding for the overall latency of ADC32RF45/8x as follows.
    <My understanding>
    * Overall latency = Latency + tpd
    * The latency is described in Table 5. This is fixed value.
    * The tpd include an analog delay. Therefore it has some variation.

    Best Regards,
    Hiroshi Katsunaga
  • 0 in reply to Hiroshi Katsunaga
    TI__Mastermind 29220 points

    Hi,

    Yes, the overall latency is the pipeline latency in clock cycles plus the tpd.  I am told by the design team that the min to max variation of tpd has not been characterized.   it is not normally requested for a device with a JESD204b interface.  There may be numerous skews in a JESD204b link, including routing length mismatches among the serial lanes, and the mechanisms for ensuring deterministic latency accounts for such skews, and any small variation in tpd would be just one of those sources of skew.  And probably a small source of skew compared to the serial links themselves.   The design team states that they would expect the tpd to vary within the range of about 4ns to 8ns, with a typical tpd of about 6ns.    May we ask why the customer is asking for this information?  (we could take the discussion off the forum if you would prefer.)

    Regards,

    Richard P.

  • 0 in reply to Richard Prentice
    Mastermind 6480 points
    Hi Richard,

    Thank you for you fast response and I'm sorry for my late reply.

    OK, I understood the estimated tpd value. (Also I understood that this value has not been characterized.)
    I understood your all comments.

    I can take the discussion off the forum.
    I have XID, however my TI e-mail address is temporary, therefore I send you e-mail from my company's e-mail address.

    Thank you for your cooperation.

    Best Regards,
    Hiroshi Katsunaga