DAC38RF83: How to estimate the latency and the latency variation

Hi Hiroshi,

The latency contribution from the DAC to the total link latency is determined by

Serdes Input to elastic buffer output + elastic buffer output to analog output + SYSREF to LMFC reset delay.

Refer to DAC38RF83 datasheet for latency values for various operating modes.

Thanks,

Eben.

Hi Eban,

Thank you for your fast response.

OK, I understood the latency items.

Is my understanding correct ?
<My understanding>
* RX SerDes Digital Delay = Fix (ex. 34UI@full rate)
* SerDes output to JESD204B elastic buffer input latency = 21 to 39 JESD clock cycles (This parameter has a variation.)
* JESD buffer to DAC output = Fix (ex. 916 DAC clock cycles@LMFSHD=44210, 8x iterpolation)
* SYSREF to JESD reset = Fix (ex. 29 JESD clock cycles@LMFSHD=44210, 8x iterpolation)

Best Regards,
Hiroshi Katsunaga

Hi Eban,

Thank you for your fast response.
OK, I understood your comments.

Thank you for your cooperation.

Best Regards,
Hiroshi Katsunaga