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ADC12J4000EVM: Help to parse ADC12J4000EVM data stream

Bing Ouyang1
Expert 1040 points
Part Number: ADC12J4000EVM
Other Parts Discussed in Thread: ADC12J4000,

I am currently setting up to use:

3760MHz clk, decimation by 4; P54=1;

Therefore the data stream is suppose to be a I/Q demodulated signal.

However, I really only set up this way to simplify the FPGA code on the TSW14J56EVM side (using 4 lanes instead of 8). What would be the way for me to still get the actual time series data once I received the raw data in the FPGA in TSW14J56EVM?

Thanks for help!

Regards, Bing

  • 0
    TI__Mastermind 43870 points

    Hi Bing

    If the ADC is configured in Decimate by 4 mode, there is no way to access the actual 12 bit time series data converted by the 12 bit ADC. The data output in this mode has passed through the complex mixer and decimation filters, resulting in an I+Q pair each with 15+15 bit resolution.

    If you only want to handle 4 lanes of data in your FPGA design you could configure the ADC into DDC Bypass mode and then only capture 4 of the 8 lanes of data. If you capture either the even or odd lanes, you will be getting every second sample converted by the ADC.

    Please refer to Table 13 in the datasheet. If you capture the Lane 0, Lane 2, Lane 4 and Lane 6 you will have all of the even numbered samples from the ADC. So if the ADC is set to 3760 MHz clock the effective sample rate will be 1880 MSPS.

    I hope this is helpful.

    Best regards,

    Jim B

  • 0 in reply to Jim Brinkhurst1
    Expert 1040 points

    Jim, thanks! One thing I want to consult you -- when I used decimation=4 mode, the PLL_LOCK flag was high in the JESD_STATUS register. When I switched to this new setting (bypass model Dev_clk = 3760MHz, FPGA clock = 188MHz, K=4), this flag now become low. I had to manually overwrite F in the FPGA design from the default of 15 to 8 to match the first entry in table 11. I used lane 0,2,4,6 as you suggested.

    I do see the data flowing through but I haven't tried to pass it yet. But I am going to follow Table 12 to do that, is that correct?

    Thanks again! Bing

  • 0 in reply to Bing Ouyang1
    TI__Mastermind 43870 points

    Hi Bing

    Decimate by 4 DDR=1 P54=1 uses the 5/4 multiplying PLL so the lock bit is relevant.

    DDC Bypass mode DDR=1 does not use the PLL. So the fact that the lock bit is not set is OK.

    Yes, use Table 12 and/or Table 13 to parse the data. The Table 13 samples you will be processing are all even samples (the ones in lanes 0, 2, 4 an 6).

    Best regards,

    Jim B

  • 0 in reply to Jim Brinkhurst1
    Expert 1040 points

    Jim,

    Thanks again. I finally got data from ADC into my Matlab variable now. But I am still having some trouble parsing the data.

    In my setup i used Table 11 entry 1,and K=4, clock = 3760, scramble bit=0. I am using the ADC12J4000 test mode, therefore I was looking for similar patterns as indicated in table 33.

    The data I have does have some patterns in it, changes every 64 bytes. However, that pattern does not seem to match Table 33... 

    A couple more related questions have:

    1) Since the interface is 128bit wide, I am still having a bit trouble to understand how it is mapped to Table 13 -- does the suffix in S1, S2... S39 indicating the order how they will be packed?

    2) In my case, since I skip every other lane (used lanes 0, 2, 4, 6), I wonder if that changes the mapping as well?

    3) I also wonder if you can clarify about the frame -- it seems the data will be sent in frames 1,2,3,4... this is irrelevant to what the K values I used to configure JESD204B?

    I am attaching a file contains portion of the raw byte data stream here for you to review (the input is the ADC test pattern).

    Thanks again, Bing

    output.txt 
    FF
00
00
FF
01
EF
0F
01
FB
00
04
5F
3F
00
C0
FF
F0
FF
00
F0
10
F0
FE
00
F0
FB
A0
F0
ED
3F
00
ED
00
F0
FF
00
FE
10
F0
FE
04
F0
FB
A0
C0
F0
3F
00
0F
00
FF
0F
EF
0F
01
F0
0F
04
5F
0F
12
C0
FF
12
FF
00
00
FF
01
EF
0F
01
FB
00
04
5F
3F
00
C0
FF
F0
FF
00
F0
10
F0
FE
00
F0
FB
A0
F0
ED
3F
00
ED
00
F0
FF
00
FE
10
F0
FE
04
F0
FB
A0
C0
F0
3F
00
0F
00
FF
0F
EF
0F
01
F0
0F
04
5F
0F
12
C0
FF
12
FF
00
00
FF
01
EF
0F
01
FB
00
04
5F
3F
00
C0
FF
F0
FF
00
F0
10
F0
FE
00
F0
FB
A0
F0
ED
3F
00
ED
F0
FF
00
F0
10
F0
FE
00
F0
FB
A0
F0
ED
3F
00
ED
00
F0
FF
00
FE
10
F0
FE
04
F0
FB
A0
C0
F0
3F
00
0F
00
FF
0F
EF
0F
01
F0
0F
04
5F
0F
12
C0
FF
12
FF
00
00
FF
01
EF
0F
01
FB
00
04
5F
3F
00
C0
FF
F0
FF
00
F0
10
F0
FE
00
F0
FB
A0
F0
ED
3F
00
ED
00
F0
FF
00
FE
10
F0
FE
04
F0
FB
A0
C0
F0
3F
00
0F
00
FF
0F
EF
0F
01
F0
0F
04
5F
0F
12
C0
FF
12
FF
00
00
FF
01
EF
0F
01
FB
00
04
5F
3F
00
C0
FF
F0
FF
00
F0
10
F0
FE
00
F0
FB
A0
F0
ED
3F
00
ED
00
F0
FF
00
FE
10
F0
FE
04
F0
FB
A0
C0
F0
3F
00
0F
00
FF
0F
EF
0F
01
F0
0F
04
5F
0F
12
C0
FF
12
FF
00
00
FF
01
EF
0F
01
FB
00
04
5F
3F
00
C0
FF
F0
FF
00
F0
10
F0
FE
00
F0
FB
A0
F0
ED
3F
00
ED
00
F0
FF
00
FE
10
F0
FE
04
F0
FB
A0
C0
F0
3F
00
0F
00
FF
0F
EF
0F
01
F0
0F
04
5F
0F
12
C0
FF
12
FF
00
00
FF
01
EF
0F
01
FB
00
04
5F
3F
00
C0
FF
F0
FF
00
F0
10
F0
FE
00
F0
FB
A0
F0
ED
3F
00
ED
00
F0
FF
00
FE
10
F0
FE
04
F0
FB
A0
C0
F0
3F
00
0F
00
FF
0F
EF
0F
01
F0
0F
04
5F
0F
12
C0
FF
12
FF
00
00
FF
01
EF
0F
01
FB
00
04
5F
3F
00
C0
FF
F0
FF
00
F0
10
F0
FE
00
F0
FB
A0
F0
ED
3F
00
ED
00
F0
FF
00
FE
10
F0
FE
04
F0
FB
A0
C0
F0
3F
00
0F
00
FF
0F
EF
0F
01
F0
0F
04
5F
0F
12
C0
FF
12
FF
00
00
FF
01
EF
0F
01
FB
00
04
5F
3F
00
C0
FF
F0
FF
00
F0
10
F0
FE
00
F0
FB
A0
F0
ED
3F
00
ED
00
F0
FF
00
FE
10
F0
FE
04
F0
FB
A0
C0
F0
3F
00
0F
00
FF
0F
EF
0F
01
F0
0F
04
5F
0F
12
C0
FF
12
FF
00
00
FF
01
EF
0F
01
FB
00
04
5F
3F
00
C0
FF
F0
FF
00
F0
10
F0
FE
00
F0
FB
A0
F0
ED
3F
00
ED
00
F0
FF
00
FE
10
F0
FE
04
F0
FB
A0
C0
F0
3F
00
0F
00
FF
0F
EF
0F
01
F0
0F
04
5F
0F
12
C0
FF
12
FF
00
00
FF
01
EF
0F
01
FB
00
04
5F
3F
00
C0
FF
F0
FF
00
F0
10
F0
FE
00
F0
FB
A0
F0
ED
3F
00
ED
00
F0
FF
00
FE
10
F0
FE
04
F0
FB
A0
C0
F0
3F
00
0F
00
FF
0F
EF
0F
01
F0
0F
04
5F
0F
12
C0
FF
12
FF
00
00
FF
01
EF
0F
01
FB
00
04
5F
3F
00
C0
FF
F0
FF
00
F0
10
F0
FE
00
F0
FB
A0
F0
ED
3F
00
ED
00
F0
FF
00
FE
10
F0
FE
04
F0
FB
A0
C0
F0
3F
00
0F
00
FF
0F
EF
0F
01
F0
0F
04
5F
0F
12
C0
FF
12
FF
00
00
FF
01
EF
0F
01
FB
00
04
5F
3F
00
C0
FF
F0
FF
00
F0
10
F0
FE
00
F0
FB
A0
F0
ED
3F
00
ED
00
F0
FF
00
FE
10
F0
FE
04
F0
FB
A0
C0
F0
3F
00
0F
00
FF
0F
EF
0F
01
F0
0F
04
5F
0F
12
C0
FF
12
FF
00
00
FF
01
EF
0F
01
FB
00
04
5F
3F
00
C0
FF
F0
FF
00
F0
10
F0
FE
00
F0
FB
A0
F0
ED
3F
00
ED
00
F0
FF
00
FE
10
F0
FE
04
F0
FB
A0
C0
F0
3F
00
0F
00
FF
0F
EF
0F
01
F0
0F
04
5F
0F
12
C0
FF
12
FF
00
00
FF
01
EF
0F
01
FB
00
04
5F
3F
00
C0
FF
F0
FF
00
F0
10
F0
FE
00
F0
FB
A0
F0
ED
3F
00
ED
00
F0
FF
00
FE
10
F0
FE
04
F0
FB
A0
C0
F0
3F
00
0F
00
FF
0F
EF
0F
01
F0
0F
04
5F
0F
12
C0
FF
12
FF
00
00
FF
01
EF
0F
01
FB
00
04
5F
3F
00
C0
FF
F0
FF
00
F0
10
F0
FE
00
F0
FB
A0
F0
ED
3F
00
ED
00
F0
FF
00
FE
10
F0
FE
04
F0
FB
A0
C0
F0
3F
00

  • 0 in reply to Bing Ouyang1
    Expert 1040 points

    Jim,

    Sorry to keep bugging you on this... I am just puzzled why I am getting some values not in Table 33. even though the pattern has a regular period of  64 byes. I checked that I did not have background cal on.

    Thanks again for your help.  

  • 0 in reply to Bing Ouyang1
    TI__Mastermind 43870 points

    Hi Bing

    The ADC12J4000 complies with the JESD204B Alignment Monitoring requirements. JESD204B transmitters must insert alignment characters into the data stream according to specific rules. The rules are different for scrambling enabled versus scrambling disabled. JESD204B receivers must monitor for alignment characters and follow specific rules to reinsert the proper equivalent data values into the final output data stream.

    If you JESD204B data receive IP is not processing the alignment characters properly that could lead to what you are seeing. Repetitive data like the ADC test pattern will cause a higher than normal number of alignment characters to be inserted.

    Please refer to "Section 5.3.3.4 Frame alignment monitoring and correction" of the JESD204B standard. (available here: www.jedec.org/sites/default/files/docs/JESD204B.pdf) Your FPGA IP vendor should also be able to help you with this.

    Best regards,

    Jim B

  • 0 in reply to Jim Brinkhurst1
    Expert 1040 points
    Jim,

    Thanks! I will check the document.

    Regards, Bing
  • 0 in reply to Bing Ouyang1
    Expert 1040 points
    Jim, since I am setting L=4 now in theJESD parameters for the TSW14J56 altera FPGA to take lanes 0,2,4,6, then should I also change M=4 as well?

    Thanks,
  • 0 in reply to Bing Ouyang1
    TI__Mastermind 43870 points

    Hi Bing

    Yes. If you had M=8 for the L=8 case, then you should have M=4 for the L=4 case.

    Best regards,

    Jim B

  • 0 in reply to Jim Brinkhurst1
    Expert 1040 points

    Jim thanks for the clarification.

    Regards,  Bing

  • 0 in reply to Jim Brinkhurst1
    Expert 1040 points

    Jim, Sorry I am still stuck with this problem... I checked with Altera and their support pointed me to check the mapping between Tx and Receiver... However, the Tx part is fixed in ADC12J4000 and since I am using TSW14J56EVM and Altera JESD204B IP, since the byte stream I referred to was captured in the FIFO, wouldn't the frame alignment be handled above this layer?

    What I am really puzzled is the that even say there is frame alignment character, the hex code "A" should not appear...

    Also, I would assume the TI firmware would have similar logic to handle the same input stream as I do here, would you point to where in the TI design this is handled?

    Thanks again, Bing

  • 0 in reply to Bing Ouyang1
    TI__Mastermind 43870 points

    Hi Bing

    Can you provide more detail on the current problem?

    For example if you are using the ADC Test Pattern mode, what is the actual data you are getting compared to what is expected on lanes 0, 2 4 and 6 from the ADC. If you are getting unexpected characters is the unexpected value random or some consistent value or values?

    Thanks,

    Jim B

  • 0 in reply to Jim Brinkhurst1
    Expert 1040 points

    Jim, the raw byte stream output is has a period of 128. I am attaching the excel spread sheet contains this information. As you can see from the hex data, there are those "illegal" codes (A, C etc.) that what puzzled me.

    Thanks again!

    Regards, Bingraw_byte_stream.xlsx

  • 0 in reply to Bing Ouyang1
    TI__Mastermind 43870 points

    Hi Bing

    If you are using Decimation = 1 you should only get the proper characters in the data stream.

    If you are using Decimation = 4 you will need to format the data into 16+16 complex values and should use one of the other ADC test patterns, like the Long Transport Test pattern, or the Ramp pattern.

    Please confirm which ADC EVM settings you are using. Can you attach a screen shot of the EVM GUI quick start tab settings that you are using?

    Regards,

    Jim B

  • 0 in reply to Jim Brinkhurst1
    Expert 1040 points

    Jim, yes I was using the bypass mode. I am attaching the screen shots and actual register file saved from the low level view GUI.

    Thanks again for your help.

    adc12j4000evm_current.pptxadc12j4000evm_current.cfg

  • 0 in reply to Bing Ouyang1
    TI__Mastermind 43870 points

    Hi Bing

    I'm not sure what the problem may be. The ADC12J4000EVM and TSW14J56EVM work properly in that mode and with that serial data rate. Here is the captured data from High Speed Data Converter Pro at 3760 MHz clock rate, in DDC Bypass mode, with ADC test pattern mode enabled.

    This has data from all lanes per Table 33 of the ADC12J4000 datasheet. In your case the sequence will not have the odd lane values, so 008, FF7, 020, FDF, 100 EFF, 400 and BFF should not appear, otherwise the sequence should be correct.

    Samples - Waveform ADC Codes - Waveform Hex
    0 0 0
    1 8 8
    2 16 10
    3 32 20
    4 64 40
    5 256 100
    6 512 200
    7 1024 400
    8 4095 FFF
    9 4087 FF7
    10 4079 FEF
    11 4063 FDF
    12 4031 FBF
    13 3839 EFF
    14 3583 DFF
    15 3071 BFF
    16 0 0
    17 8 8
    18 16 10
    19 32 20
    20 64 40
    21 256 100
    22 512 200
    23 1024 400
    24 4095 FFF
    25 4087 FF7
    26 4079 FEF
    27 4063 FDF
    28 4031 FBF
    29 3839 EFF
    30 3583 DFF
    31 3071 BFF
    32 0 0
    33 8 8
    34 16 10
    35 32 20
    36 64 40
    37 256 100
    38 512 200
    39 1024 400
    40 4095 FFF
    41 4087 FF7
    42 4079 FEF
    43 4063 FDF
    44 4031 FBF
    45 3839 EFF
    46 3583 DFF
    47 3071 BFF
    48 0 0
    49 8 8
    50 16 10
    51 32 20
    52 64 40
    53 256 100
    54 512 200
    55 1024 400
    56 4095 FFF
    57 4087 FF7
    58 4079 FEF
    59 4063 FDF
    60 4031 FBF
    61 3839 EFF
    62 3583 DFF
    63 3071 BFF
    64 0 0
    65 8 8
    66 16 10
    67 32 20
    68 64 40
    69 256 100
    70 512 200
    71 1024 400
    72 4095 FFF
    73 4087 FF7
    74 4079 FEF
    75 4063 FDF
    76 4031 FBF
    77 3839 EFF
    78 3583 DFF
    79 3071 BFF

    Samples - Unwrap Waveform    ADC Codes - Unwrap Waveform    Samples - Waveform    ADC Codes - Waveform    
            0    0    
            1    8    
            2    16    
            3    32    
            4    64    
            5    256    
            6    512    
            7    1024    
            8    4095    
            9    4087    
            10    4079    
            11    4063    
            12    4031    
            13    3839    
            14    3583    
            15    3071    
            16    0    
            17    8    
            18    16    
            19    32    
            20    64    
            21    256    
            22    512    
            23    1024    
            24    4095    
            25    4087    
            26    4079    
            27    4063    
            28    4031    
            29    3839    
            30    3583    
            31    3071    
            32    0    
            33    8    
            34    16    
            35    32    
            36    64    
            37    256    
            38    512    
            39    1024    
            40    4095    
            41    4087    
            42    4079    
            43    4063    
            44    4031    
            45    3839    
            46    3583    
            47    3071    
            48    0    
            49    8    
            50    16    
            51    32    
            52    64    
            53    256    
            54    512    
            55    1024    
            56    4095    
            57    4087    
            58    4079    
            59    4063    
            60    4031    
            61    3839    
            62    3583    
            63    3071    
            64    0    
            65    8    
            66    16    
            67    32    
            68    64    
            69    256    
            70    512    
            71    1024    
            72    4095    
            73    4087    
            74    4079    
            75    4063    
            76    4031    
            77    3839    
            78    3583    
            79    3071    
            80    0    
            81    8    
            82    16    
            83    32    
            84    64    
            85    256    
            86    512    
            87    1024    
            88    4095    
            89    4087    
            90    4079    
            91    4063    
            92    4031    
            93    3839    
            94    3583    
            95    3071    
            96    0    
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  • 0 in reply to Jim Brinkhurst1
    Expert 1040 points

    Jim,

    I tested ramp pattern and I can confirm I had the same JESD data corruption issue.

    Thanks, Bing

  • 0 in reply to Bing Ouyang1
    Expert 1040 points

    Jim,

    I am currently using 4GHz devclk on ADC12J4000 and in bypass mode. On TSW14J56EVM, when I configure the PLL for the JESD clock, should I set the "Reference Clock Frequency" (highlighted) to 400MHz?

    Thanks, Bing 

  • 0 in reply to Bing Ouyang1
    TI__Mastermind 43870 points

    Hi Bing

    At 4 GHz clock rate in DDC Bypass mode, the lane rate is 8 Gbit/sec.

    We configure the FPGA clock frequency to be LineRate/40 which is 200 MHz in this case.

    Let me know if you need anything else.

    Best regards,

    Jim B

  • 0 in reply to Jim Brinkhurst1
    Expert 1040 points

    Jim,

    I will configure the FPGA clock to 200MHz (output clock 1).  I am referring to the input cloc or "Reference Clock Frequency"

    My question arised from reading your answer in this thread: https://e2e.ti.com/support/data_converters/high_speed_data_converters/f/68/t/506503. 

    "At 4 GHz clock, the lane rate is 8 Gbit/sec. Therefore the clocks to the FPGA should be as follows:

    GT REFCLK = 8000 / 20 = 400 MHz

    Core Clock = 8000 / 40 = 200 MHz"

    I understand that was a Xilinx board, but is GT REFCLK the same as "Reference Clock Frequency" when I configure the PLL IP core in Arria V GZ?

    Thanks again

  • 0 in reply to Bing Ouyang1
    TI__Mastermind 43870 points

    Hi Bing

    The other thread you referenced above is specific to the Xilinx JESD204B transceiver requirements. In the Xilinx platform 2 separate clocks are needed, one for the FPGA fabric and one for the PLL reference clock.

    For the TSW14J56 (Altera) case both sections of the FPGA use the same frequency clock. For LineRate >=3100 Mbit/sec we send a clock at LineRate/40.
     For LineRate <3100 Mbit/sec we send a clock at LineRate/10.

    Best regards,

    Jim B