DAC3174: DAC 3174 issues at higher frequency

Hi,

if you are not doing any register programming, then what are you doing to reset the FIFO pointers inside the DAC?  The address pointers in the device for the write side of the FIFO need to be reset with a SYNC input, and the address pointers for the read side of the FIFO need to be reset with an ALIGN input.     And these two events need to happen at about the same time to ensure that the data coming out of the FIFO is about 4 words behind the data going into the FIFO.    If you are not planning to synchronize multiple DAC devices to maintain uniform latency across all channels then you don't need to use the ALIGN signal, but you will still need to have an ALIGN 'event' by substituting a SYNC 'event' in place of the ALIGN 'event' by setting the sync_only register bit and using the SYNC input.  This lets the SYNC input be used to reset address pointers in both sides of the FIFO and the ALIGN input pins could be left unused.   And if you don't wish to have a source for the SYNC input, you can set the sif_sync_ena bit in the device and then set the sif_sync bit to zero and then on another register write set the sif_sync to one.  Then the SYNC input pins could also be left unused.   You only have to reset the FIFO address pointers once after power up, but it has to be at least once and the reset pin doesn't do it. 

Regards,

Richard P.

Hi Richard

 
                        I have done what you asked to modify. I am using only Dac clock as well as Data clock. I am not using SYNC and allign. I am writing following registers

Address Value

00          x"04ed"

01         x"601e"

01         x"603e"

But the problem is, once in a while spectrum is not coming clean when I am operating at 300 MHz. There is no issue when operation is at 150 MHz.

What could be done for this.

Hi,

since you are using the sif_sync now, you would not need to have the sync input buffer enable in Config0 bit 3.   But it sounds to me more like you are having timing issues getting the data latched into the DAC if it works at low sample rates and not at higher sample rates.   Config3 lets you adjust the timing of the data and sync relative to the clock input, you can add delay to the data busses or add delay to the clock signal to adjust for timing out of the FPGA.   I expect you are taking default register values for Config3.  You could start by incrementing the value for the clock delay one by one to see if the issue resolves, or if not then incrementing the values for the data busses to see if the issue resolves.   There is also the option to enable the pattern verification feature and have the FPGA send a repeating 8-sample pattern to the DAC and let the DAC compare the pattern against pre-stored patterns to check for errors on the digital bus, but to use this feature you would have to do a SPI read back to check for timing errors.   But a quicker test would be to just try incrementing the delay values.   the field clkdlyb is the one that delays the clock in full-word interface mode, and clkdlya delays the SYNC if needed.   The two datadly fields would be used with the same values to delay the data busses.

Regards,

Richard P. 

Hi Richard

I tried delaying the data with all the possible combination available but could not see the solution. I asked altera also, whether some issue in there in nco ipcore .