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ADS54RF63: Issue at high speed operation

Vikas Kumar40
Intellectual 630 points
Part Number: ADS54RF63
Other Parts Discussed in Thread: LMK01020,

Hi,

      I am using ADS54RF63. The device is working fine at 200 MHz. But when I am operating at 400 MHz, the data is getting corrupted at ADC pin itself. I am using LMK01020 for clocking and DRY for data capturing.

  • 0
    TI__Mastermind 29220 points

    Hi,

    The devices are production tested at up to 550Msps, and the ADS54RF63 EVM is known to operate with our FPGA capture cards such as TSW1400 or TSW1405.  I was using one of these EVMs just yesterday with the TSW1405 FPGA card.   I would need to know much more information about just how you are using the device and just what it is you are seeing when you observe a problem.    Are you using the device on our EVM or on your own design. into your own FPGA?    You are aware of the source-aligned timing of the DRY relative to data, such that you have to have a 90 degree phase delay of DRY inside your FPGA before you can use it to latch the data?    The DRY signal does not leave the ADC with any setup/hold time provided at the ADC,. so in order to get valid setup/hold timing into the FPGA you would need to have some delay element or PLL for the DRY signal inside the FPGA.

    Regards,

    Richard P.

  • 0 in reply to Richard Prentice
    Intellectual 630 points

    Hi Richard

                        I am aware of the DRY signal and I am using FPGA PLL to delay the clock by 90 degree compared to DRY. Then I am using Ipcore to get the rising edge as well falling edge data. After that I am using 400 MHz to combine the data. The concept is working fine at 200 MHz where I am getting SNR of 61. But at 400, SNR is just 14.

  • 0 in reply to Vikas Kumar40
    Intellectual 630 points

    Hi Richard

                     I am having a doubt. The data captured at rising as well falling edge of DRy, is it valid 12 bit data or its like, on rising edge ,  I will get odd bits and falling edge, even bits ??