• State
  • Locked Locked
  • Replies 1 reply
  • Subscribers 46 subscribers
  • Views 342 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADC32RF45: Inter-channel signal time offset caused by new ADC32RFxxEVM GUI

MatthewBridges
Prodigy 15 points
Part Number: ADC32RF45

Hi,

I am running a test using an SMA100A signal generator in pulse modulation mode. I have a minicircuits splitter which I splits the sig gens output into channel A and B of an ADC32RF45EVM.

I set up the ADC and LMK Clock Chip using the old GUI (ADC32RFxxEVM_revD_GUI) with the following parameters

  • Fs = 2949.12MSps
  • DDC set to 4X decimation IQ
  • DDC frequency is set to 0

Signal Generator is set to:

  • 20MHz Pulse modulation 0dBm

I then capture and plot a set of samples. This is shown below.

The first plot is IQ for first ADC Channel and the second is IQ for the second ADC Channel. [Disclaimer: The time scale is in in samples not seconds. I forgot to change the title] 

I repeat the exact same test using the new GUI (ADC32RFxx EVM GUI) to set up the ADC and Clock.

In this case the plot (as shown below) contains a time offset between Channel A and B.

I would appreciate any feedback or ideas as to why this may occur.

Kind regards,

Matthew Bridges

  • 0
    TI__Mastermind 29220 points

    Hi,

    May I ask what the revision of the EVM is, please?  The EVM that is currently in stock is the revision E circuit board, with production silicon installed.   The previous revisions of EVM had pre-production silicon installed.

    The configuration files that came with the revD SPI GUI were created for the pre-production silicon.   The latest SPI GUI has config files for production silicon, and with them a folder named pre-production silicon that contains the config files that had previously come with the revD GUI.  

    There have been a few changes to the SPI GUI underlying code such that there could be some issues in using a config file from an older GUI with the new version of GUI unless the cfg file were edited to account for those changes.  Using the cfg files that came with the installer for that GUI would be fine - such as using the cfg files that came with the revD GUI when running the revD GUI and using the cfg files that came with the new GUI when running the new GUI.    Copying files of from the older to the newer could have an issue in a few cases. 

    May I ask to see the config files you are using for the two cases?  I have not seen a mismatch in latency between the data from channel A and from channel B as you are showing.  I have seen the two channels stay aligned - with the new GUI and new config files.  

    one other possible source of such mismatch would be if the release point of the JESD204b IP in the FPGA got off by one LMFC cycle for the two channels, so that the FPGA buffer were releasing the data skewed.   In your system - what is your SYSREF frequency and does the skew between the two channels happen to be one SYSREF cycle perchance?   Although I do not know why there should be something in our cfg files that would cause the FPGA to have an issue.   But it might be a clue if the skew you see did happen to be one SYSREF cycle.

    Regards,

    Richard P.