I'm driving the DAC2904 from an FPGA and have individual control of the CLK and WRT lines.
A) Assuming that both WRT and CLK are rising edge sensitive rather than level sensitive, the implication of the timing table is that for maximum margin I would update the data lines almost simultaneously with the falling edge of WRT/CLK. But the diagram is drawn with the pulse centered on the data valid window, implying level sensitivity. Assuming an 8 ns, 50% duty cycle clock, what is the optimal timing to drive the DAC?
B) If I wanted to skew WRT and CLK in order to shave a few ns off of the latency, there is the t_CW spec of "Delay Rising CLK Edge to Rising WRT Edge". This seems backwards; if I was only going to pulse each one time it would have to be WRT then CLK. So what is my minimum timing margin to do that? That table line could be read as requiring 2 ns from WRT to CLK, but is certainly not clear to me.
Thanks,
Rob
