ADS54J54EVM: Using ADS54J54EVM with TSW14J50

Ivan,

There is a TSW14J50EVM User's Guide for this board under the TSW14J50EVM product folder on the TI website. What LMF mode were you using? What is your ADC sample rate and Serdes rate? What is the status of all of the LED's? Is your 5V power supply capable of sourcing at least 2 Amps? The TSW14J50 can only support 6.5Gbps when using 4 lanes and around 5Gbps when using 8.

Regards,

Jim  

Hi Jim
The power supply, yes it is able to deliver the 5V and 2 amps, in fact is the source that comes with the kit of the ADS54J54EVM.
The status of all LEDs is as follows:
LEDs on the ADS54J54EVM
ON-> D10 (5V IN)
ON-> D1 (LMK LOCKED)
ON-> D4 (PLL2 LOCKED)
OFF-> D13 (STAT 0)
OFF-> D5 (STAT 1)
OFF-> D3 (JESD_SYNC) (the LED I tell you does not turn on in step 7)

LED's of the TSW14J50
ON-> D28 (FPGA CONF DONE)
ON-> D10 (5V IN)
ON-> D8 (MEM_CAL_F)
OFF-> D7 (MEM_CAL_P)
OFF-> D6 (MEM_IN_DN)
ON-> D5 (SPI_CLK)
BLINK-> D4 (RX HB)
ON-> D3 (RX SYNC #)
BLINK-> D2 (TX HB)
OFF -> D1 (TX SYNC #)
   
In the ADS54J54 EVM GUI software I am using the configuration file ADS54J54_500M_841.cfg, it is assumed that with this file you have a sample rate of 500MSPS without decimation, below I put the screens of its configuration parameters, according to the JESD Configuration screen, L = 4, F = 1, K = 32

Hi,

I will look into this on my bench shortly.   I did some digging into this, and found that the EVM was checked out with the TSW14J50 last year before the ini files were added to HSDCPro for the ADS54J54 support for the J50.  But I also see something in the setup that concerns me that maybe the use of the EVM with the capture card may not be reliable and I need to check that out.   (What I am looking at is that the ADS54J54 requires two SYNC signals from the FPGA, one for channels A and B and the other for channels C and D.   There *are* two sets of pin definitions through the FMC connector for SYNC and alternate SYNC, but the default FPGA firmware for the alternate SYNC is single ended CMOS, not LVDS.  For the TSW14J56 we had a firmware available that made the alternate SYNC be LVDS.  What I need to find out is if the single ended CMOS alternate SYNC will sometimes work into the LVDS inputs on the ADC and sometimes not - that is my hypothesis at present.  That would explain the fact that this setup passed checkout recently. )

Regards,

Richard P.

Hi Richard
ust to ask what happened to this situation

Regards,
Ivan

Hi,

sorry for the delay.   I did power up the EVM on my bench and used it without problem using both the TSW14J56 and the TSW14J50.   And that is in spite of my concern about the need for the second SYNC signal from the FPGA to the ADC.  My understanding is that the FPGA is driving the alternate SYNC, but not as an LVDS signal.  But I haven't probed the signal on the EVM with the scope yet - so I will go do that.  I don't have any other suspicions as to what the issue might be other than the alternate SYNC, as I used the normal EVM SPI GUI and the config files that come with the GUI. 

Regards,

Richard P.

Richard,
Did you use the ADS54J54_500M_841.cfg configuration file?
Are the parameters the same as the screens that I put above?
If it is not the same configuration file, could you send me the file you used?

Regards
Ivan

Hi Richard
Just to ask you about the last message I sent,
Regards
Ivan

Richard

I am waiting for your answer

Hi Richard
Just to ask you about the last message I sent,
Regards
Ivan

Hi,

I have had my bench tied up with a debug issue and haven't been able to bring up the ADS54J54 EVM lately.  I will get back to it, and by the end of the week is what I am planning for.  I apologize for the delay.

Regards,

Richard P.

Hi, I still waiting

Richard,
It has already spent a month and a half and you do not respond

OK Steve, thank you

I will do as you say and let you know

e2e wouldn't let me put the .rbf file up by itself. so for clarity's sake, you will need to pull the TSW14J50_Firmward.rbf out of the folder I sent and put only that file in C:\Program Files (x86)\Texas Instruments\High Speed Data Converter Pro\14J50 Details\Firmware

Good luck! let me know how it goes.

best regards,
-Steve Wilson

Hello Ivan,

I want to check in with you and see how things are going. Did the new firmware solve your problem?

Best regards,

-Steve

Hello Ivan,

We are interested to hear if the firmware update solved your problem. Let us know if you are able to get a capture.

-Steve Wilson

Hello Steve
I just used the ADS54J54EVM with the TSW14J50 and the new HSDC Pro firmware that you sent and the problem is still the same.
I think the problem is in the EVM GUI software, maybe the configuration file ADS54J54_500M_841.cfg should be modified to match the new firmware of the HSDC pro

Hi,

The new firmware that Steve provided was expected to be the most likely reason for why a setup would work properly in one instance and maybe not work properly in another.   So we have to keep looking.  Are you available to set up a WebEx session where I could see what you are seeing and I could have the EVM operational on my bench and let you see what my setup looks like when it is working properly?    That might be a quicker way to see many aspects of your setup compared to my setup, such as what version of HSDCPro you are using, whether the proper firmware name shows up in the lower right corner of HSDCPro, and a bunch of other such things. 

The configuration files that come with the SPI GUI for the ADC EVM were developed initially for the TSW14J56 and were checked out - both the 8 lane configuration and the 4 lane configuration.   Later these two modes of operation were added to the TSW14J50 but they were also checked out at that time and we see these modes working on our bench at this time on both the TSW14J56 and TSW14J50.  The ini files for the TSW14J50 were specifically created to not require different configuration files for the ADC EVM - that is, we used the same settings for the L, M, F, S and K value, and once the K value was set in the ADC config file and the matching value set for the HSDCPro ini file then the clocking and SYSREF become the same for both setups as well.  

But maybe a WebEx session could shed some light on what is going on.  While we see about setting that up, may I ask what the markings are on the top of the ADC that is soldered on to the ADC EVM/    What part number is inked on the top of the ADC, and the likes below the part number that indicate the device assembly lot code?

Regards,

Richard P.

Hi Richard
The number inked on the ADC is:
XADS54J54
20141203
I attach a photo so that you can see it

Hi,

Thank you.   That matches the EVM that we are using in the lab, and eliminates one possibility that I had considered about maybe an error in assembly.  So I suggest we set up a WebEx so we can take a good look at each other's setup.

Thanks,

Richard P.

Hi Richard
I do not have a portable webcam.
I only have the webcam in my Laptop, on the other hand, I do not speak English fluently (which will be a problem).
Can you make a video showing all the steps?
And then I make another video so that you see the step where the LED does not turn on

Hi,

I webex would not need a webcam, it would just be that you could view my computer desktop while I was setting up the EVM GUI and HSDCPro to see what I was doing and then see the capture in HSDCPro.  And then if I transferred control of the webex to you and you allowed viewing of your desktop I could see what you are doing with your SPI GUI and HSDCPro. 

I have recently bought a Camtasia license so I can set up the EVM and HSDCPro and capture and catch it all in a Camtasia video and then I can send that to you, so yes that would be fine. 

I have not been too worried about the LED for the SYNC indication because that LED is driven by an output from the FPGA on the capture card, and I am not sure that our recent FPGA firmware of the last few revisions have been too worried about keeping that feature.  But when I set up I will take note of that LED and see.  

What revision of HSDCPro are you using, please?

Thanks,

Richard P.

Hi Richard

I am using the HSDC Pro v4.50

Hi Richard

Just to ask you, When will you send the video?

Hi,

Shortly.  My copy of the EVM was being used for something else recently and I had to have it put back to stock configuration.  That was done this morning.

Regards,

Richard P.

Hi,

I brought up the ADS54J54 EVM on my bench with the TSW14J50 and created a short video of the process.   Please follow the drop box link below.  In the drop-box link I out the mp4 video, as well as the firmware needed to make the capture work.  (The firmware you recently tried as well.  I put it in the drop-box for good measure.)  Also, it occurred to me while setting this up that there was another way of getting the capture to work with the TSW14J50 using the default firmware that comes with the current release of HSDCPro.    I created a new ini file for the HSDCPro that only uses two of the channels of the ADS54J54 and I named that ini file for channels A and B of the ADS54J54.   Since the default firmware with HSDCPro at the moment only drives one of the SYNC signals from the FPGA back to the ADC for channels A and B, I made a special ini file for that mode.  The ini file essentially pretends the data converter is only a 2 channel device for the moment.   The new firmware drives the second alternate SYNC signal from the FPGA back to the ADC as an LVDS signal for channels C and D, so this is the firmware needed for all four channels of the original device selection for the ADS54J54.  So - two ways to get the capture to work: new firmware to make all four channels capture or new device ini file to make the default firmware work with 2 channels.   I copied the alternate firmware into the Firmware folder of the 14J50 Details folder where the HSDCPro is installed.  I copied the new device ini file to the ADC Files folder of the 14J50 Details folder.

https://txn.box.com/s/n9s1xiciu03w15memprd4b81cdm00ow5

Regards,

Richard P.

Hello Richard

I tried the files you sent and they did not work, I downloaded version 4.7 of HSDCPro and it worked fine.

There is only one problem, when feeding the same signal to two channels at the same time, the combinations with channel B are out of phase, ie A and B, B and C, B and D.

If the remaining combinations are used, the captured signals are in phase

I sent the screenshots for you to observe this situation

regards

Ivan

Hi Richard

Did yo mean remove R49 and then install it in R9?

Regards

ah, yes. I drew it correctly in the drawing but stated it backwards in the text. Remove R49 and install it on R9. And install J12. it is pretty tough to remove one of those SMA connectors by hand to move it over from J2 to J12. We usually just add a new connector and leave the old one in place when we wish to install the other side of the pair. But maybe with a hot air pencil above and a hot plate below the SMA could be removed but you don't want to overheat the transformers too much.

Thanks,
Richard P.